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authorAlan Hourihane <alanh@tungstengraphics.com>2008-09-11 17:32:18 +0100
committerAlan Hourihane <alanh@tungstengraphics.com>2008-09-11 17:32:18 +0100
commit47ad296a183929c2007c35c60d722b4ac680417d (patch)
tree62bcc7af01606d32d7f137ccf8f342c9b0a6774a /src/mesa/drivers/dri/i965
parentb6458225039ef4cf5c91080e7547ed73fb264c46 (diff)
parent4d42c5bebf8740ebfc15571d24b6c92f79e09263 (diff)
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/mesa into gallium-0.2
Conflicts: src/mesa/drivers/dri/i915/intel_ioctl.c src/mesa/main/texstore.c src/mesa/tnl/t_vp_build.c src/mesa/vbo/vbo_exec_draw.c
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/Makefile3
-rw-r--r--src/mesa/drivers/dri/i965/brw_cc.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_state.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c13
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs_state.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf_state.c20
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_state.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_glsl.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_sampler_state.c12
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c31
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c36
l---------src/mesa/drivers/dri/i965/intel_ioctl.c1
17 files changed, 84 insertions, 85 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 8fa205e79f..c2d555cd0c 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -13,7 +13,6 @@ DRIVER_SOURCES = \
intel_decode.c \
intel_depthstencil.c \
intel_fbo.c \
- intel_ioctl.c \
intel_mipmap_tree.c \
intel_regions.c \
intel_screen.c \
@@ -91,6 +90,8 @@ ASM_SOURCES =
DRIVER_DEFINES = -I../intel -I../intel/server
+DRI_LIB_DEPS += -ldrm_intel
+
include ../Makefile.template
symlinks:
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index d662cf7521..0458bf5983 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -255,12 +255,12 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
NULL, NULL);
/* Emit CC viewport relocation */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0,
- 0,
- offsetof(struct brw_cc_unit_state, cc4),
- brw->cc.vp_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ 0,
+ 0,
+ offsetof(struct brw_cc_unit_state, cc4),
+ brw->cc.vp_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index ae904c6253..51045f9188 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -119,12 +119,12 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0,
- clip.thread0.grf_reg_count << 1,
- offsetof(struct brw_clip_unit_state, thread0),
- brw->clip.prog_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ 0,
+ clip.thread0.grf_reg_count << 1,
+ offsetof(struct brw_clip_unit_state, thread0),
+ brw->clip.prog_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index d43b52c2c7..95d798238d 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -39,7 +39,6 @@
#include "brw_state.h"
#include "brw_fallback.h"
-#include "intel_ioctl.h"
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
diff --git a/src/mesa/drivers/dri/i965/brw_draw.h b/src/mesa/drivers/dri/i965/brw_draw.h
index 2a3e0c1c5b..e0bba589d5 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.h
+++ b/src/mesa/drivers/dri/i965/brw_draw.h
@@ -31,7 +31,6 @@
#include "mtypes.h" /* for GLcontext... */
#include "vbo/vbo.h"
-#include "dri_bufmgr.h"
struct brw_context;
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 0122d18f82..465239f195 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -39,7 +39,6 @@
#include "brw_state.h"
#include "brw_fallback.h"
-#include "intel_ioctl.h"
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
#include "intel_tex.h"
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6b97f8b170..0bfbec9d14 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -513,6 +513,8 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.predicate_control = BRW_PREDICATE_NORMAL;
insn->header.mask_control = BRW_MASK_ENABLE;
+ if (!p->single_program_flow)
+ insn->header.thread_control = BRW_THREAD_SWITCH;
p->current->header.predicate_control = BRW_PREDICATE_NONE;
@@ -538,6 +540,8 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = if_insn->header.execution_size;
insn->header.mask_control = BRW_MASK_ENABLE;
+ if (!p->single_program_flow)
+ insn->header.thread_control = BRW_THREAD_SWITCH;
/* Patch the if instruction to point at this instruction.
*/
@@ -579,6 +583,7 @@ void brw_ENDIF(struct brw_compile *p,
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = patch_insn->header.execution_size;
insn->header.mask_control = BRW_MASK_ENABLE;
+ insn->header.thread_control = BRW_THREAD_SWITCH;
assert(patch_insn->bits3.if_else.jump_count == 0);
@@ -617,7 +622,7 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p)
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
insn->bits3.if_else.pad0 = 0;
return insn;
}
@@ -631,7 +636,7 @@ struct brw_instruction *brw_CONT(struct brw_compile *p)
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
insn->bits3.if_else.pad0 = 0;
return insn;
}
@@ -655,7 +660,7 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
insn->header.execution_size = execute_size;
insn->header.predicate_control = BRW_PREDICATE_NONE;
/* insn->header.mask_control = BRW_MASK_ENABLE; */
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
return insn;
}
@@ -694,7 +699,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
/* insn->header.mask_control = BRW_MASK_ENABLE; */
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
p->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index ff2e3ab059..633e17cc9d 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -106,11 +106,11 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- gs.thread0.grf_reg_count << 1,
- offsetof(struct brw_gs_unit_state, thread0),
- brw->gs.prog_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ gs.thread0.grf_reg_count << 1,
+ offsetof(struct brw_gs_unit_state, thread0),
+ brw->gs.prog_bo);
}
return bo;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 2478872b82..07d0b4c798 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -251,18 +251,18 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
NULL, NULL);
/* Emit SF program relocation */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- sf.thread0.grf_reg_count << 1,
- offsetof(struct brw_sf_unit_state, thread0),
- brw->sf.prog_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ sf.thread0.grf_reg_count << 1,
+ offsetof(struct brw_sf_unit_state, thread0),
+ brw->sf.prog_bo);
/* Emit SF viewport relocation */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
- offsetof(struct brw_sf_unit_state, sf5),
- brw->sf.vp_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
+ offsetof(struct brw_sf_unit_state, sf5),
+ brw->sf.vp_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index d1d319d92e..7d4fd467b1 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -33,7 +33,6 @@
#include "brw_context.h"
#include "brw_state.h"
-#include "dri_bufmgr.h"
#include "intel_batchbuffer.h"
/* This is used to initialize brw->state.atoms[]. We could use this
diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c
index 258c6260fb..ab6393420a 100644
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -42,7 +42,6 @@
#include "texmem.h"
#include "intel_context.h"
-#include "intel_ioctl.h"
#include "intel_regions.h"
#include "intel_tex.h"
#include "brw_context.h"
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 909b942610..24bf5567bd 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -115,11 +115,11 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
NULL, NULL);
/* Emit VS program relocation */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- vs.thread0.grf_reg_count << 1,
- offsetof(struct brw_vs_unit_state, thread0),
- brw->vs.prog_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ vs.thread0.grf_reg_count << 1,
+ offsetof(struct brw_vs_unit_state, thread0),
+ brw->vs.prog_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 305100f883..8dce40f25b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -850,20 +850,20 @@ static void emit_sop(struct brw_wm_compile *c,
struct brw_reg dst, src0, src1;
int i;
- brw_push_insn_state(p);
for (i = 0; i < 4; i++) {
if (mask & (1<<i)) {
dst = get_dst_reg(c, inst, i, 1);
src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
+ brw_push_insn_state(p);
brw_CMP(p, brw_null_reg(), cond, src0, src1);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_MOV(p, dst, brw_imm_f(0.0));
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_MOV(p, dst, brw_imm_f(1.0));
+ brw_pop_insn_state(p);
}
}
- brw_pop_insn_state(p);
}
static void emit_slt(struct brw_wm_compile *c,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 08d01823de..e47dbe8b10 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -303,12 +303,12 @@ static void upload_wm_samplers( struct brw_context *brw )
if (!brw->attribs.Texture->Unit[i]._ReallyEnabled)
continue;
- intel_bo_emit_reloc(brw->wm.sampler_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0,
- i * sizeof(struct brw_sampler_state) +
- offsetof(struct brw_sampler_state, ss2),
- brw->wm.sdc_bo[i]);
+ dri_bo_emit_reloc(brw->wm.sampler_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0,
+ i * sizeof(struct brw_sampler_state) +
+ offsetof(struct brw_sampler_state, ss2),
+ brw->wm.sdc_bo[i]);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f97d0dc285..61fe97a463 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -34,7 +34,6 @@
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
-#include "dri_bufmgr.h"
#include "brw_wm.h"
/***********************************************************************
@@ -199,28 +198,28 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
NULL, NULL);
/* Emit WM program relocation */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- wm.thread0.grf_reg_count << 1,
- offsetof(struct brw_wm_unit_state, thread0),
- brw->wm.prog_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ wm.thread0.grf_reg_count << 1,
+ offsetof(struct brw_wm_unit_state, thread0),
+ brw->wm.prog_bo);
/* Emit scratch space relocation */
if (key->total_scratch != 0) {
- intel_bo_emit_reloc(bo,
- 0, 0,
- wm.thread2.per_thread_scratch_space,
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.scratch_buffer);
+ dri_bo_emit_reloc(bo,
+ 0, 0,
+ wm.thread2.per_thread_scratch_space,
+ offsetof(struct brw_wm_unit_state, thread2),
+ brw->wm.scratch_buffer);
}
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
- offsetof(struct brw_wm_unit_state, wm4),
- brw->wm.sampler_bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
+ offsetof(struct brw_wm_unit_state, wm4),
+ brw->wm.sampler_bo);
}
return bo;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index af1401b34b..8fcd50924f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -138,7 +138,7 @@ static GLuint translate_tex_format( GLuint mesa_format, GLenum depth_mode )
case MESA_FORMAT_SRGB_DXT1:
return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
- case MESA_FORMAT_Z24_S8:
+ case MESA_FORMAT_S8_Z24:
return BRW_SURFACEFORMAT_I24X8_UNORM;
default:
@@ -234,11 +234,11 @@ brw_create_texture_surface( struct brw_context *brw,
if (key->bo) {
/* Emit relocation to surface contents */
- intel_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_SAMPLER, 0,
- 0,
- offsetof(struct brw_surface_state, ss1),
- key->bo);
+ dri_bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_SAMPLER, 0,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ key->bo);
}
return bo;
}
@@ -374,13 +374,13 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
* them both. We might be able to figure out from other state
* a more restrictive relocation to emit.
*/
- intel_bo_emit_reloc(brw->wm.surf_bo[unit],
- I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_SAMPLER,
- I915_GEM_DOMAIN_RENDER,
- 0,
- offsetof(struct brw_surface_state, ss1),
- region_bo);
+ dri_bo_emit_reloc(brw->wm.surf_bo[unit],
+ I915_GEM_DOMAIN_RENDER |
+ I915_GEM_DOMAIN_SAMPLER,
+ I915_GEM_DOMAIN_RENDER,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ region_bo);
}
}
}
@@ -420,11 +420,11 @@ brw_wm_get_binding_table(struct brw_context *brw)
/* Emit binding table relocations to surface state */
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
- intel_bo_emit_reloc(bind_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0,
- i * sizeof(GLuint),
- brw->wm.surf_bo[i]);
+ dri_bo_emit_reloc(bind_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0,
+ i * sizeof(GLuint),
+ brw->wm.surf_bo[i]);
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_ioctl.c b/src/mesa/drivers/dri/i965/intel_ioctl.c
deleted file mode 120000
index effd0f378d..0000000000
--- a/src/mesa/drivers/dri/i965/intel_ioctl.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_ioctl.c \ No newline at end of file