diff options
author | Eric Anholt <eric@anholt.net> | 2011-01-10 10:01:12 -0800 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2011-01-10 17:21:10 -0800 |
commit | 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 (patch) | |
tree | 220862ba5058742e9330550c995c687737fd07bf /src/mesa/drivers/dri/i965 | |
parent | da0c0dbab060416452e7c96415abef91ec7d64f4 (diff) |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 11 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 |
3 files changed, 15 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 66adc49cc9..9ac0713a1d 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -67,7 +67,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel, i945_miptree_layout_2d(intel, mt, tiling, 6); - for (level = 0; level < mt->levels; level++) { + for (level = mt->first_level; level <= mt->last_level; level++) { for (q = 0; q < 6; q++) { intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch); } @@ -101,7 +101,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel, pack_x_pitch = width; pack_x_nr = 1; - for (level = 0; level < mt->levels; level++) { + for (level = mt->first_level ; level <= mt->last_level ; level++) { GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6; GLint x = 0; GLint y = 0; diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index f830e25626..30672b4251 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -115,7 +115,6 @@ struct wm_sampler_key { struct wm_sampler_entry { GLenum tex_target; GLenum wrap_r, wrap_s, wrap_t; - uint32_t base_level; float maxlod, minlod; float lod_bias; float max_aniso; @@ -244,7 +243,14 @@ static void brw_update_sampler_state(struct brw_context *brw, sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - sampler->ss0.base_level = U_FIXED(key->base_level, 1); + /* Set BaseMipLevel, MaxLOD, MinLOD: + * + * XXX: I don't think that using firstLevel, lastLevel works, + * because we always setup the surface state as if firstLevel == + * level zero. Probably have to subtract firstLevel from each of + * these: + */ + sampler->ss0.base_level = U_FIXED(0, 1); sampler->ss1.max_lod = U_FIXED(CLAMP(key->maxlod, 0, 13), 6); sampler->ss1.min_lod = U_FIXED(CLAMP(key->minlod, 0, 13), 6); @@ -286,7 +292,6 @@ brw_wm_sampler_populate_key(struct brw_context *brw, entry->wrap_s = texObj->WrapS; entry->wrap_t = texObj->WrapT; - entry->base_level = texObj->BaseLevel; entry->maxlod = texObj->MaxLod; entry->minlod = texObj->MinLod; entry->lod_bias = texUnit->LodBias + texObj->LodBias; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 4570af66cd..e921d8a9a1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -196,15 +196,15 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */ surf.ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */ - /* mip_count is #levels - 1 */ surf.ss2.mip_count = intelObj->_MaxLevel - tObj->BaseLevel; - surf.ss2.width = intelObj->mt->width0 - 1; - surf.ss2.height = intelObj->mt->height0 - 1; + surf.ss2.width = firstImage->Width - 1; + surf.ss2.height = firstImage->Height - 1; brw_set_surface_tiling(&surf, intelObj->mt->region->tiling); surf.ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1; - surf.ss3.depth = intelObj->mt->depth0 - 1; - surf.ss4.min_lod = tObj->BaseLevel; + surf.ss3.depth = firstImage->Depth - 1; + surf.ss4.min_lod = 0; + if (tObj->Target == GL_TEXTURE_CUBE_MAP) { surf.ss0.cube_pos_x = 1; surf.ss0.cube_pos_y = 1; |