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authorEric Anholt <eric@anholt.net>2008-06-26 13:45:31 -0700
committerEric Anholt <eric@anholt.net>2008-06-26 15:29:28 -0700
commit93f701bc3619864ac6f067d37212e96545a57e16 (patch)
tree8f84c57cd3cbfdd1f74477640a792b18c71db377 /src/mesa/drivers/dri/intel/intel_blit.c
parentf6abe8f0f2fba3073b58b96ed38aae163c765b4a (diff)
intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.
Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_blit.c')
-rw-r--r--src/mesa/drivers/dri/intel/intel_blit.c25
1 files changed, 10 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 80d11a01b7..84a455d1cb 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -159,14 +159,10 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
ADVANCE_BATCH();
}
- /* Emit a flush so that, on systems where we don't have automatic flushing
- * set (such as 965), the results all land on the screen in a timely
- * fashion.
+ /* Flush the rendering and the batch so that the results all land on the
+ * screen in a timely fashion.
*/
- BEGIN_BATCH(1, IGNORE_CLIPRECTS);
- OUT_BATCH(MI_FLUSH);
- ADVANCE_BATCH();
-
+ intel_batchbuffer_emit_mi_flush(intel->batch);
intel_batchbuffer_flush(intel->batch);
}
@@ -372,10 +368,7 @@ intelEmitCopyBlit(struct intel_context *intel,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
- BEGIN_BATCH(1, NO_LOOP_CLIPRECTS);
- OUT_BATCH(MI_FLUSH);
- ADVANCE_BATCH();
- intel_batchbuffer_flush(intel->batch);
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
@@ -556,7 +549,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
}
}
}
- intel_batchbuffer_flush(intel->batch);
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
@@ -594,7 +587,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
(8 * 4) +
(3 * 4) +
dwords,
- NO_LOOP_CLIPRECTS );
+ REFERENCES_CLIPRECTS );
opcode = XY_SETUP_BLT_CMD;
if (cpp == 4)
@@ -616,7 +609,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
if (dst_tiled)
blit_cmd |= XY_DST_TILED;
- BEGIN_BATCH(8 + 3, NO_LOOP_CLIPRECTS);
+ BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
OUT_BATCH(opcode);
OUT_BATCH(br13);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
@@ -636,5 +629,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
intel_batchbuffer_data( intel->batch,
src_bits,
dwords * 4,
- NO_LOOP_CLIPRECTS );
+ REFERENCES_CLIPRECTS );
+
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}