diff options
| author | Eric Anholt <eric@anholt.net> | 2008-07-01 15:09:24 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2008-07-01 16:14:08 -0700 |
| commit | e74f54793e45dd2e36474f6fc527456647f32efd (patch) | |
| tree | 6c84ade0bf15ba5b7d7d76536adf84c61fa215c2 /src/mesa/drivers/dri/intel/intel_context.c | |
| parent | f059a3302260075e9cfd35649dc3877726291d8d (diff) | |
intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.
It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling. It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_context.c')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 46acf79721..33b8843e33 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -697,6 +697,9 @@ intelInitContext(struct intel_context *intel, intel->no_rast = 1; } + intel->tiling_swizzle_mode = driQueryOptioni(&intel->optionCache, + "swizzle_mode"); + /* Disable all hardware rendering (skip emitting batches and fences/waits * to the kernel) */ |