intel-gem: Fix Y-tiling span setup.

The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode.  Instead, guess the correct
tiling in screen setup.

Also, fix the Y-tiling pitch setup.  The pitch to the next tile in Y is
32 scanlines, not 8.

1 files changed, 10 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index bc0b579429..3a3ce68c59 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -376,7 +376,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
  * not a user-created renderbuffer.
  */
 struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat, int tiling)
+intel_create_renderbuffer(intelScreenPrivate *intelScreen,
+			  GLenum intFormat, enum tiling_mode tiling)
 {
    GET_CURRENT_CONTEXT(ctx);
 
@@ -449,8 +450,14 @@ intel_create_renderbuffer(GLenum intFormat, int tiling)
    irb->Base.Delete = intel_delete_renderbuffer;
    irb->Base.AllocStorage = intel_alloc_window_storage;
    irb->Base.GetPointer = intel_get_pointer;
-   /* This sets the Get/PutRow/Value functions */
-   intel_set_span_functions(&irb->Base, tiling);
+   /* This sets the Get/PutRow/Value functions.  In classic mode, all access
+    * is through the aperture and will be swizzled by the fence registers, so
+    * we don't need the span functions to perfom tile swizzling
+    */
+   if (intelScreen->ttm)
+      intel_set_span_functions(&irb->Base, tiling);
+   else
+      intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
 
    return irb;
 }