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| author | Zack Rusin <zackr@vmware.com> | 2010-03-15 15:24:38 -0400 |
|---|---|---|
| committer | Zack Rusin <zackr@vmware.com> | 2010-03-15 15:24:38 -0400 |
| commit | 275c4bd3643d773210780cb8d578ca84f2604684 (patch) | |
| tree | 8266edc39d4253ac0f2a0ecd41f560f3d815bb5c /src/mesa/drivers/dri/intel/intel_mipmap_tree.c | |
| parent | c5c5cd7132e18f4aad8e73d8ee879f8823c4c1e7 (diff) | |
| parent | d0b35352ed27b1e66785c45ee95a352ed06b47ce (diff) | |
Merge remote branch 'origin/master' into gallium_draw_llvm
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_mipmap_tree.c')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index cb5a341050..4f14946ec7 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -119,8 +119,7 @@ intel_miptree_create(struct intel_context *intel, struct intel_mipmap_tree *mt; uint32_t tiling; - if (intel->use_texture_tiling && compress_byte == 0 && - intel->intelScreen->kernel_exec_fencing) { + if (intel->use_texture_tiling && compress_byte == 0) { if (intel->gen >= 4 && (base_format == GL_DEPTH_COMPONENT || base_format == GL_DEPTH_STENCIL_EXT)) @@ -238,11 +237,11 @@ int intel_miptree_pitch_align (struct intel_context *intel, pitch = ALIGN(pitch * mt->cpp, pitch_align); #ifdef I915 - /* XXX: At least the i915 seems very upset when the pitch is a multiple - * of 1024 and sometimes 512 bytes - performance can drop by several - * times. Go to the next multiple of the required alignment for now. + /* Do a little adjustment to linear allocations so that we avoid + * hitting the same channel of memory for 2 different pages when + * reading a 2x2 subspan or doing bilinear filtering. */ - if (!(pitch & 511) && + if (tiling == I915_TILING_NONE && !(pitch & 511) && (pitch + pitch_align) < (1 << ctx->Const.MaxTextureLevels)) pitch += pitch_align; #endif |