diff options
| author | Eric Anholt <eric@anholt.net> | 2008-10-19 17:46:41 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2008-10-28 13:23:33 -0700 |
| commit | 0cade4de4f74f6b0e86fb6622e2fc370c73fd840 (patch) | |
| tree | ae6c62ddbda5c3139c7e08e0d7682d949d53ab0c /src/mesa/drivers/dri/intel/intel_reg.h | |
| parent | e92a457ac0030e48f5260dc2ac00ca283be7d7ad (diff) | |
intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_reg.h')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h index c21f408093..81a7386e42 100644 --- a/src/mesa/drivers/dri/intel/intel_reg.h +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -29,6 +29,8 @@ #define CMD_2D (0x2 << 29) #define CMD_3D (0x3 << 29) +#define MI_NOOP (CMD_MI | 0) + #define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) #define MI_FLUSH (CMD_MI | (4 << 23)) @@ -44,6 +46,9 @@ #define _3DSTATE_LOAD_STATE_IMMEDIATE_1 (CMD_3D | (0x1d<<24) | (0x04<<16)) #define I1_LOAD_S(n) (1<<(4+n)) +#define _3DSTATE_DRAWRECT_INFO (CMD_3D | (0x1d<<24) | (0x80<<16) | 0x3) +#define _3DSTATE_DRAWRECT_INFO_I965 (CMD_3D | (3 << 27) | (1 << 24) | 0x2) + /** @{ * * PIPE_CONTROL operation, a combination MI_FLUSH and register write with |