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authorEric Anholt <eric@anholt.net>2009-06-12 08:44:40 -0700
committerEric Anholt <eric@anholt.net>2009-06-17 20:19:19 -0700
commitbd10f0e84f1491363d76d92dcbd410ab5cc43dbe (patch)
tree5ffeada7cd79fc5f507e4e6ab1779d3fa8058f27 /src/mesa/drivers/dri/intel/intel_regions.c
parentb165fa7d45e230f9e61fcf3a09babf0c61c67319 (diff)
i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.
This may hurt if miptree relayout occurs, since we can't blit Y tiled objects. But it corrects depth tests on FBOs using textures.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_regions.c')
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 49bcb3c1dd..7c3b483836 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -189,7 +189,7 @@ intel_region_alloc(struct intel_context *intel,
pitch, buffer);
if (tiling != I915_TILING_NONE) {
- assert(((pitch * cpp) & 511) == 0);
+ assert(((pitch * cpp) & 127) == 0);
drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
}