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authorEric Anholt <eric@anholt.net>2008-07-02 09:10:21 -0700
committerEric Anholt <eric@anholt.net>2008-07-02 09:10:21 -0700
commit19f585a3cf65887e249d630fe43e83e7e7618dfa (patch)
treefcd55e2f48d45d0dac1e708adf5f0ba32763ea40 /src/mesa/drivers/dri/intel/intel_span.c
parente74f54793e45dd2e36474f6fc527456647f32efd (diff)
intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_span.c')
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 8d7d913ca9..6138b262f4 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -168,7 +168,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
int x_tile_number, y_tile_number;
int tile_off, tile_base;
- tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
+ tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
x += intel->drawX;
y += intel->drawY;
@@ -181,7 +181,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
x_tile_number = xbyte >> 7;
y_tile_number = y >> 5;
- tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + (x_tile_off & 0xf);
+ tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
+ (x_tile_off & 0xf);
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;
@@ -670,7 +671,7 @@ intelInitSpanFuncs(GLcontext * ctx)
* These are used for the software fallbacks.
*/
void
-intel_set_span_functions(struct gl_renderbuffer *rb, int tiling)
+intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
{
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */