diff options
author | José Fonseca <jfonseca@vmware.com> | 2010-01-08 15:42:57 +0000 |
---|---|---|
committer | José Fonseca <jfonseca@vmware.com> | 2010-01-08 15:42:57 +0000 |
commit | 080c40ab32b2abd6d8381b4a0cc143d36a1652b2 (patch) | |
tree | e173767ebc5a82d81b9fc086449d915e29348976 /src/mesa/drivers/dri/intel/intel_span.c | |
parent | 9cdf6f025b2ed55cfb13dd09f870f01d0c7947d3 (diff) | |
parent | a1de400e8de06a80ab140bb0fa950e990607572d (diff) |
Merge remote branch 'origin/master' into lp-binning
Conflicts:
src/gallium/auxiliary/util/u_surface.c
src/gallium/drivers/llvmpipe/Makefile
src/gallium/drivers/llvmpipe/SConscript
src/gallium/drivers/llvmpipe/lp_bld_arit.c
src/gallium/drivers/llvmpipe/lp_bld_flow.c
src/gallium/drivers/llvmpipe/lp_bld_interp.c
src/gallium/drivers/llvmpipe/lp_clear.c
src/gallium/drivers/llvmpipe/lp_context.c
src/gallium/drivers/llvmpipe/lp_context.h
src/gallium/drivers/llvmpipe/lp_draw_arrays.c
src/gallium/drivers/llvmpipe/lp_jit.c
src/gallium/drivers/llvmpipe/lp_jit.h
src/gallium/drivers/llvmpipe/lp_prim_vbuf.c
src/gallium/drivers/llvmpipe/lp_setup.c
src/gallium/drivers/llvmpipe/lp_setup_point.c
src/gallium/drivers/llvmpipe/lp_state.h
src/gallium/drivers/llvmpipe/lp_state_blend.c
src/gallium/drivers/llvmpipe/lp_state_derived.c
src/gallium/drivers/llvmpipe/lp_state_fs.c
src/gallium/drivers/llvmpipe/lp_state_sampler.c
src/gallium/drivers/llvmpipe/lp_state_surface.c
src/gallium/drivers/llvmpipe/lp_tex_cache.c
src/gallium/drivers/llvmpipe/lp_tex_cache.h
src/gallium/drivers/llvmpipe/lp_tex_sample.h
src/gallium/drivers/llvmpipe/lp_tile_cache.c
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_span.c')
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_span.c | 190 |
1 files changed, 110 insertions, 80 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index dcfcad1d95..605734d8e5 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -29,7 +29,6 @@ #include "main/macros.h" #include "main/mtypes.h" #include "main/colormac.h" -#include "main/texformat.h" #include "intel_buffers.h" #include "intel_fbo.h" @@ -132,18 +131,6 @@ pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val) dri_bo_subdata(irb->region->buffer, offset, 1, &val); } -static uint32_t -z24s8_to_s8z24(uint32_t val) -{ - return (val << 24) | (val >> 8); -} - -static uint32_t -s8z24_to_z24s8(uint32_t val) -{ - return (val >> 24) | (val << 8); -} - static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb, int x, int y) { @@ -163,6 +150,9 @@ static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb, int x_tile_number, y_tile_number; int tile_off, tile_base; + x += irb->region->draw_x; + y += irb->region->draw_y; + tile_stride = (irb->region->pitch * irb->region->cpp) << 3; xbyte = x * irb->region->cpp; @@ -218,6 +208,9 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, int x_tile_number, y_tile_number; int tile_off, tile_base; + x += irb->region->draw_x; + y += irb->region->draw_y; + tile_stride = (irb->region->pitch * irb->region->cpp) << 5; xbyte = x * irb->region->cpp; @@ -273,8 +266,11 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, unsigned int num_cliprects; \ struct drm_clip_rect *cliprects; \ int x_off, y_off; \ + int pitch = irb->region->pitch * irb->region->cpp; \ + void *buf = irb->region->buffer->virtual; \ GLuint p; \ (void) p; \ + (void)buf; (void)pitch; /* unused for non-gttmap. */ \ intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); /* XXX FBO: this is identical to the macro in spantmp2.h except we get @@ -296,7 +292,6 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, #define Y_FLIP(_y) ((_y) * yScale + yBias) -/* XXX with GEM, these need to tell the kernel */ #define HW_LOCK() #define HW_UNLOCK() @@ -339,7 +334,7 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, #include "intel_spantmp.h" /* x8r8g8b8 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_BGRA +#define INTEL_PIXEL_FMT GL_BGR #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset) #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v) @@ -354,6 +349,9 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, unsigned int num_cliprects; \ struct drm_clip_rect *cliprects; \ int x_off, y_off; \ + int pitch = irb->region->pitch * irb->region->cpp; \ + void *buf = irb->region->buffer->virtual; \ + (void)buf; (void)pitch; /* unused for non-gttmap. */ \ intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); @@ -366,20 +364,22 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, #define INTEL_TAG(name) name##_z16 #include "intel_depthtmp.h" -/* z24 depthbuffer functions. */ +/* z24x8 depthbuffer functions. */ #define INTEL_VALUE_TYPE GLuint #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d) #define INTEL_READ_DEPTH(offset) pread_32(irb, offset) -#define INTEL_TAG(name) name##_z24 +#define INTEL_TAG(name) name##_z24_x8 #include "intel_depthtmp.h" -/* z24s8 depthbuffer functions. */ -#define INTEL_VALUE_TYPE GLuint -#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d)) -#define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset)) -#define INTEL_TAG(name) name##_z24_s8 -#include "intel_depthtmp.h" +/** + ** 8-bit stencil function (XXX FBO: This is obsolete) + **/ +/* XXX */ +#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d) +#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3); +#define TAG(x) intel_gttmap_##x##_z24_s8 +#include "stenciltmp.h" /** ** 8-bit stencil function (XXX FBO: This is obsolete) @@ -413,6 +413,9 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb) if (irb == NULL || irb->region == NULL) return; + if (intel->intelScreen->kernel_exec_fencing) + drm_intel_gem_bo_map_gtt(irb->region->buffer); + intel_set_span_functions(intel, rb); } @@ -425,7 +428,10 @@ intel_renderbuffer_unmap(struct intel_context *intel, if (irb == NULL || irb->region == NULL) return; - clear_span_cache(irb); + if (intel->intelScreen->kernel_exec_fencing) + drm_intel_gem_bo_unmap_gtt(irb->region->buffer); + else + clear_span_cache(irb); rb->GetRow = NULL; rb->PutRow = NULL; @@ -494,6 +500,8 @@ intel_map_unmap_framebuffer(struct intel_context *intel, else intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped); } + + intel_check_front_buffer_rendering(intel); } /** @@ -509,7 +517,6 @@ intelSpanRenderStart(GLcontext * ctx) GLuint i; intelFlush(&intel->ctx); - LOCK_HARDWARE(intel); for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { @@ -545,8 +552,6 @@ intelSpanRenderFinish(GLcontext * ctx) intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE); if (ctx->ReadBuffer != ctx->DrawBuffer) intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE); - - UNLOCK_HARDWARE(intel); } @@ -605,17 +610,56 @@ intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb) { struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; - uint32_t tiling; + uint32_t tiling = irb->region->tiling; + + if (intel->intelScreen->kernel_exec_fencing) { + switch (irb->Base.Format) { + case MESA_FORMAT_RGB565: + intel_gttmap_InitPointers_RGB565(rb); + break; + case MESA_FORMAT_ARGB4444: + intel_gttmap_InitPointers_ARGB4444(rb); + break; + case MESA_FORMAT_ARGB1555: + intel_gttmap_InitPointers_ARGB1555(rb); + break; + case MESA_FORMAT_XRGB8888: + intel_gttmap_InitPointers_xRGB8888(rb); + break; + case MESA_FORMAT_ARGB8888: + intel_gttmap_InitPointers_ARGB8888(rb); + break; + case MESA_FORMAT_Z16: + intel_gttmap_InitDepthPointers_z16(rb); + break; + case MESA_FORMAT_X8_Z24: + intel_gttmap_InitDepthPointers_z24_x8(rb); + break; + case MESA_FORMAT_S8_Z24: + /* There are a few different ways SW asks us to access the S8Z24 data: + * Z24 depth-only depth reads + * S8Z24 depth reads + * S8Z24 stencil reads. + */ + if (rb->Format == MESA_FORMAT_S8_Z24) { + intel_gttmap_InitDepthPointers_z24_x8(rb); + } else if (rb->Format == MESA_FORMAT_S8) { + intel_gttmap_InitStencilPointers_z24_s8(rb); + } + break; + default: + _mesa_problem(NULL, + "Unexpected MesaFormat %d in intelSetSpanFunctions", + irb->Base.Format); + break; + } + return; + } /* If in GEM mode, we need to do the tile address swizzling ourselves, * instead of the fence registers handling it. */ - if (intel->ttm) - tiling = irb->region->tiling; - else - tiling = I915_TILING_NONE; - - switch (irb->texformat->MesaFormat) { + switch (irb->Base.Format) { case MESA_FORMAT_RGB565: switch (tiling) { case I915_TILING_NONE: @@ -658,35 +702,33 @@ intel_set_span_functions(struct intel_context *intel, break; } break; + case MESA_FORMAT_XRGB8888: + switch (tiling) { + case I915_TILING_NONE: + default: + intelInitPointers_xRGB8888(rb); + break; + case I915_TILING_X: + intel_XTile_InitPointers_xRGB8888(rb); + break; + case I915_TILING_Y: + intel_YTile_InitPointers_xRGB8888(rb); + break; + } + break; case MESA_FORMAT_ARGB8888: - if (rb->AlphaBits == 0) { /* XXX: Need xRGB8888 Mesa format */ - /* 8888 RGBx */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_xRGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_xRGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_xRGB8888(rb); - break; - } - } else { - /* 8888 RGBA */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_ARGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_ARGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_ARGB8888(rb); - break; - } + /* 8888 RGBA */ + switch (tiling) { + case I915_TILING_NONE: + default: + intelInitPointers_ARGB8888(rb); + break; + case I915_TILING_X: + intel_XTile_InitPointers_ARGB8888(rb); + break; + case I915_TILING_Y: + intel_YTile_InitPointers_ARGB8888(rb); + break; } break; case MESA_FORMAT_Z16: @@ -703,39 +745,27 @@ intel_set_span_functions(struct intel_context *intel, break; } break; + case MESA_FORMAT_X8_Z24: case MESA_FORMAT_S8_Z24: /* There are a few different ways SW asks us to access the S8Z24 data: * Z24 depth-only depth reads * S8Z24 depth reads * S8Z24 stencil reads. */ - if (rb->_ActualFormat == GL_DEPTH_COMPONENT24) { - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitDepthPointers_z24(rb); - break; - case I915_TILING_X: - intel_XTile_InitDepthPointers_z24(rb); - break; - case I915_TILING_Y: - intel_YTile_InitDepthPointers_z24(rb); - break; - } - } else if (rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) { + if (rb->Format == MESA_FORMAT_S8_Z24) { switch (tiling) { case I915_TILING_NONE: default: - intelInitDepthPointers_z24_s8(rb); + intelInitDepthPointers_z24_x8(rb); break; case I915_TILING_X: - intel_XTile_InitDepthPointers_z24_s8(rb); + intel_XTile_InitDepthPointers_z24_x8(rb); break; case I915_TILING_Y: - intel_YTile_InitDepthPointers_z24_s8(rb); + intel_YTile_InitDepthPointers_z24_x8(rb); break; } - } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) { + } else if (rb->Format == MESA_FORMAT_S8) { switch (tiling) { case I915_TILING_NONE: default: |