diff options
| author | Eric Anholt <eric@anholt.net> | 2008-07-02 09:10:21 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2008-07-02 09:10:21 -0700 |
| commit | 19f585a3cf65887e249d630fe43e83e7e7618dfa (patch) | |
| tree | fcd55e2f48d45d0dac1e708adf5f0ba32763ea40 /src/mesa/drivers/dri/intel/intel_span.h | |
| parent | e74f54793e45dd2e36474f6fc527456647f32efd (diff) | |
intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.
Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_span.h')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_span.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h index c56e5e1611..1b47c2829c 100644 --- a/src/mesa/drivers/dri/intel/intel_span.h +++ b/src/mesa/drivers/dri/intel/intel_span.h @@ -33,10 +33,7 @@ extern void intelInitSpanFuncs(GLcontext * ctx); extern void intelSpanRenderFinish(GLcontext * ctx); extern void intelSpanRenderStart(GLcontext * ctx); -extern void intel_set_span_functions(struct gl_renderbuffer *rb, int tiling); - -#define INTEL_TILE_NONE 0 -#define INTEL_TILE_X 1 -#define INTEL_TILE_Y 2 +extern void intel_set_span_functions(struct gl_renderbuffer *rb, + enum tiling_mode tiling); #endif |