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authorEric Anholt <eric@anholt.net>2009-06-03 16:40:20 +0000
committerEric Anholt <eric@anholt.net>2009-06-04 14:00:43 +0000
commit1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e (patch)
tree2cd5c5303ec85edfc47ab8f80e60a88134f461e0 /src/mesa/drivers/dri/intel/intel_tex_layout.h
parent165ae5e2fb57bdb64b4cf01271b4effeb811f675 (diff)
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45, and experiments with 915GM indicate that it'll be around a 20% win there. Currently, 915-class hardware is seriously hurt by the fact that we use fence regs to control the tiling even for 3D instructions that could live without them, so we spend a bunch of time waiting on previous rendering in order to pull fences off. Thus, the texture_tiling driconf option defaults off there for now.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_tex_layout.h')
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index dbc90e6f9b..7bc25b6bcb 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h
@@ -38,5 +38,7 @@ static GLuint minify( GLuint d )
return MAX2(1, d>>1);
}
-extern void i945_miptree_layout_2d( struct intel_context *intel, struct intel_mipmap_tree *mt );
+extern void i945_miptree_layout_2d(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ uint32_t tiling);
extern GLuint intel_compressed_alignment(GLenum);