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authorEric Anholt <eric@anholt.net>2007-12-15 16:12:17 -0800
committerEric Anholt <eric@anholt.net>2007-12-16 11:26:19 -0800
commitc0b4257aa9ba783674ccf7162799385734dff211 (patch)
tree33d0bbdcd5f2b31660420e82f4b9f99b0e5790ca /src/mesa/drivers/dri/intel/intel_tex_validate.c
parent659baa3f25275b622dad626992af60f3c9ea6d66 (diff)
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for bringing us closer to PBO support. It also disables SGIS_generate_mipmap, which didn't seem to be working before anyway, according to the lodbias demo.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_tex_validate.c')
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_validate.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index af18c26d55..8df66ad445 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -40,6 +40,7 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj)
firstLevel = lastLevel = tObj->BaseLevel;
}
else {
+#ifdef I915
firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5);
firstLevel = MAX2(firstLevel, tObj->BaseLevel);
lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5);
@@ -47,6 +48,18 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj)
lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
lastLevel = MIN2(lastLevel, tObj->MaxLevel);
lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
+#else
+ /* Currently not taking min/max lod into account here, those
+ * values are programmed as sampler state elsewhere and we
+ * upload the same mipmap levels regardless. Not sure if
+ * this makes sense as it means it isn't possible for the app
+ * to use min/max lod to reduce texture memory pressure:
+ */
+ firstLevel = tObj->BaseLevel;
+ lastLevel = MIN2(tObj->BaseLevel + baseImage->MaxLog2,
+ tObj->MaxLevel);
+ lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
+#endif
}
break;
case GL_TEXTURE_RECTANGLE_NV:
@@ -211,8 +224,15 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
}
}
+#ifdef I915
+ /* XXX: what is this flush about?
+ * On 965, it causes a batch flush in the middle of the state relocation
+ * emits, which means that the eventual rendering doesn't have all of the
+ * required relocations in place.
+ */
if (need_flush)
intel_batchbuffer_flush(intel->batch);
+#endif
return GL_TRUE;
}