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authorEric Anholt <eric@anholt.net>2010-03-04 15:47:19 -0800
committerEric Anholt <eric@anholt.net>2010-03-04 16:56:32 -0800
commitbb35000b4b6dfe60048b2f5d60bc102c4a7fd791 (patch)
tree48e044b630db2136f3d7e63f0d85dfe1b9a03a6e /src/mesa/drivers/dri/intel
parent7cbc4c07ee85782d5da3e2db3c4e072ca498ff07 (diff)
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This means we now require 2.6.29, which seems fair given that it's a year old and we've removed support for non-KMS already in the last release of 2D.
Diffstat (limited to 'src/mesa/drivers/dri/intel')
-rw-r--r--src/mesa/drivers/dri/intel/intel_blit.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_buffer_objects.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c6
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h21
-rw-r--r--src/mesa/drivers/dri/intel/intel_depthtmp.h64
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c3
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.h3
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c3
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c6
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c9
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.h1
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c451
-rw-r--r--src/mesa/drivers/dri/intel/intel_spantmp.h67
13 files changed, 69 insertions, 581 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 6d6af86347..f2769aa3e8 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -122,8 +122,8 @@ intelEmitCopyBlit(struct intel_context *intel,
intel_prepare_render(intel);
if (pass >= 2) {
- intel_bo_map_gtt_preferred(intel, dst_buffer, GL_TRUE);
- intel_bo_map_gtt_preferred(intel, src_buffer, GL_FALSE);
+ drm_intel_gem_bo_map_gtt(dst_buffer);
+ drm_intel_gem_bo_map_gtt(src_buffer);
_mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
cpp,
dst_pitch,
@@ -132,8 +132,8 @@ intelEmitCopyBlit(struct intel_context *intel,
(GLubyte *)src_buffer->virtual + src_offset,
src_pitch,
src_x, src_y);
- intel_bo_unmap_gtt_preferred(intel, src_buffer);
- intel_bo_unmap_gtt_preferred(intel, dst_buffer);
+ drm_intel_gem_bo_unmap_gtt(src_buffer);
+ drm_intel_gem_bo_unmap_gtt(dst_buffer);
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 312866d865..8fe3a0e6f3 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -285,7 +285,7 @@ intel_bufferobj_map(GLcontext * ctx,
return NULL;
}
- if (write_only && intel->intelScreen->kernel_exec_fencing) {
+ if (write_only) {
drm_intel_gem_bo_map_gtt(intel_obj->buffer);
intel_obj->mapped_gtt = GL_TRUE;
} else {
@@ -379,8 +379,7 @@ intel_bufferobj_map_range(GLcontext * ctx,
intel_obj->range_map_bo = drm_intel_bo_alloc(intel->bufmgr,
"range map",
length, 64);
- if (!(access & GL_MAP_READ_BIT) &&
- intel->intelScreen->kernel_exec_fencing) {
+ if (!(access & GL_MAP_READ_BIT)) {
drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo);
intel_obj->mapped_gtt = GL_TRUE;
} else {
@@ -393,8 +392,7 @@ intel_bufferobj_map_range(GLcontext * ctx,
return obj->Pointer;
}
- if (!(access & GL_MAP_READ_BIT) &&
- intel->intelScreen->kernel_exec_fencing) {
+ if (!(access & GL_MAP_READ_BIT)) {
drm_intel_gem_bo_map_gtt(intel_obj->buffer);
intel_obj->mapped_gtt = GL_TRUE;
} else {
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index ec379a77ac..d6a1ba6952 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -755,12 +755,6 @@ intelInitContext(struct intel_context *intel,
}
intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
"texture_tiling");
- if (intel->use_texture_tiling &&
- !intel->intelScreen->kernel_exec_fencing) {
- fprintf(stderr, "No kernel support for execution fencing, "
- "disabling texture tiling\n");
- intel->use_texture_tiling = GL_FALSE;
- }
intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
intel->prim.primitive = ~0;
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index d20d44497e..22736a9327 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -475,25 +475,4 @@ is_power_of_two(uint32_t value)
return (value & (value - 1)) == 0;
}
-static INLINE void
-intel_bo_map_gtt_preferred(struct intel_context *intel,
- drm_intel_bo *bo,
- GLboolean write)
-{
- if (intel->intelScreen->kernel_exec_fencing)
- drm_intel_gem_bo_map_gtt(bo);
- else
- drm_intel_bo_map(bo, write);
-}
-
-static INLINE void
-intel_bo_unmap_gtt_preferred(struct intel_context *intel,
- drm_intel_bo *bo)
-{
- if (intel->intelScreen->kernel_exec_fencing)
- drm_intel_gem_bo_unmap_gtt(bo);
- else
- drm_intel_bo_unmap(bo);
-}
-
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_depthtmp.h b/src/mesa/drivers/dri/intel/intel_depthtmp.h
deleted file mode 100644
index a9c75d44cf..0000000000
--- a/src/mesa/drivers/dri/intel/intel_depthtmp.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Eric Anholt <eric@anholt.net>
- *
- */
-
-/**
- * Wrapper around the depthtmp.h macrofest to generate spans code for
- * all the tiling styles.
- */
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) \
- (*(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual + \
- NO_TILE(_x, _y)) = d)
-#define READ_DEPTH(d, _x, _y) \
- d = *(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual + \
- NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_gttmap_##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(NO_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(X_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(X_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_XTile_##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(Y_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(Y_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_YTile_##x)
-#include "depthtmp.h"
-
-#undef INTEL_VALUE_TYPE
-#undef INTEL_WRITE_DEPTH
-#undef INTEL_READ_DEPTH
-#undef INTEL_TAG
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index b388a3de2e..a429f8d003 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -70,9 +70,6 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
ASSERT(irb);
- if (irb->span_cache != NULL)
- free(irb->span_cache);
-
if (intel && irb->region) {
intel_region_release(&irb->region);
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 586dbbbb25..72413f7369 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -40,9 +40,6 @@ struct intel_renderbuffer
{
struct gl_renderbuffer Base;
struct intel_region *region;
-
- uint8_t *span_cache;
- unsigned long span_cache_offset;
};
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index a20ea5afdb..4f14946ec7 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -119,8 +119,7 @@ intel_miptree_create(struct intel_context *intel,
struct intel_mipmap_tree *mt;
uint32_t tiling;
- if (intel->use_texture_tiling && compress_byte == 0 &&
- intel->intelScreen->kernel_exec_fencing) {
+ if (intel->use_texture_tiling && compress_byte == 0) {
if (intel->gen >= 4 &&
(base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL_EXT))
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index e3c0635e5b..f042bcbc28 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -118,8 +118,7 @@ intel_region_map(struct intel_context *intel, struct intel_region *region)
if (region->pbo)
intel_region_cow(intel, region);
- if (region->tiling != I915_TILING_NONE &&
- intel->intelScreen->kernel_exec_fencing)
+ if (region->tiling != I915_TILING_NONE)
drm_intel_gem_bo_map_gtt(region->buffer);
else
dri_bo_map(region->buffer, GL_TRUE);
@@ -134,8 +133,7 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region)
{
_DBG("%s %p\n", __FUNCTION__, region);
if (!--region->map_refcount) {
- if (region->tiling != I915_TILING_NONE &&
- intel->intelScreen->kernel_exec_fencing)
+ if (region->tiling != I915_TILING_NONE)
drm_intel_gem_bo_unmap_gtt(region->buffer);
else
dri_bo_unmap(region->buffer);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 959ccfb8b1..9ff76c4803 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -416,10 +416,11 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
return GL_FALSE;
}
- if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences))
- intelScreen->kernel_exec_fencing = !!num_fences;
- else
- intelScreen->kernel_exec_fencing = GL_FALSE;
+ if (!intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences) ||
+ num_fences == 0) {
+ fprintf(stderr, "[%s: %u] Kernel 2.6.29 required.\n", __func__, __LINE__);
+ return GL_FALSE;
+ }
drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 1ce476daca..5863093f00 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -46,7 +46,6 @@ struct intel_screen
GLboolean no_vbo;
dri_bufmgr *bufmgr;
- GLboolean kernel_exec_fencing;
struct _mesa_HashTable *named_regions;
/**
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 2fcb2d843c..fb5c01bc4d 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -43,218 +43,6 @@ static void
intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb);
-#define SPAN_CACHE_SIZE 4096
-
-static void
-get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
-{
- if (irb->span_cache == NULL) {
- irb->span_cache = malloc(SPAN_CACHE_SIZE);
- irb->span_cache_offset = -1;
- }
-
- if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
- irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
- dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
- SPAN_CACHE_SIZE, irb->span_cache);
- }
-}
-
-static void
-clear_span_cache(struct intel_renderbuffer *irb)
-{
- irb->span_cache_offset = -1;
-}
-
-static uint32_t
-pread_32(struct intel_renderbuffer *irb, uint32_t offset)
-{
- get_span_cache(irb, offset);
-
- return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static uint32_t
-pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
-{
- get_span_cache(irb, offset);
-
- return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
- 0xff000000;
-}
-
-static uint16_t
-pread_16(struct intel_renderbuffer *irb, uint32_t offset)
-{
- get_span_cache(irb, offset);
-
- return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static uint8_t
-pread_8(struct intel_renderbuffer *irb, uint32_t offset)
-{
- get_span_cache(irb, offset);
-
- return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static void
-pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
-{
- clear_span_cache(irb);
-
- dri_bo_subdata(irb->region->buffer, offset, 4, &val);
-}
-
-static void
-pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
-{
- clear_span_cache(irb);
-
- dri_bo_subdata(irb->region->buffer, offset, 3, &val);
-}
-
-static void
-pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
-{
- clear_span_cache(irb);
-
- dri_bo_subdata(irb->region->buffer, offset, 2, &val);
-}
-
-static void
-pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
-{
- clear_span_cache(irb);
-
- dri_bo_subdata(irb->region->buffer, offset, 1, &val);
-}
-
-static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
- int x, int y)
-{
- return (y * irb->region->pitch + x) * irb->region->cpp;
-}
-
-/*
- * Deal with tiled surfaces
- */
-
-static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
- int x, int y)
-{
- int tile_stride;
- int xbyte;
- int x_tile_off, y_tile_off;
- int x_tile_number, y_tile_number;
- int tile_off, tile_base;
-
- x += irb->region->draw_x;
- y += irb->region->draw_y;
-
- tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
-
- xbyte = x * irb->region->cpp;
-
- x_tile_off = xbyte & 0x1ff;
- y_tile_off = y & 7;
-
- x_tile_number = xbyte >> 9;
- y_tile_number = y >> 3;
-
- tile_off = (y_tile_off << 9) + x_tile_off;
-
- switch (irb->region->bit_6_swizzle) {
- case I915_BIT_6_SWIZZLE_NONE:
- break;
- case I915_BIT_6_SWIZZLE_9:
- tile_off ^= ((tile_off >> 3) & 64);
- break;
- case I915_BIT_6_SWIZZLE_9_10:
- tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
- break;
- case I915_BIT_6_SWIZZLE_9_11:
- tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
- break;
- case I915_BIT_6_SWIZZLE_9_10_11:
- tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
- ((tile_off >> 5) & 64);
- break;
- default:
- fprintf(stderr, "Unknown tile swizzling mode %d\n",
- irb->region->bit_6_swizzle);
- exit(1);
- }
-
- tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
-
-#if 0
- printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
- x, y, tile_off, tile_base,
- tile_off + tile_base,
- irb->region->pitch, tile_stride);
-#endif
-
- return tile_base + tile_off;
-}
-
-static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
- int x, int y)
-{
- int tile_stride;
- int xbyte;
- int x_tile_off, y_tile_off;
- int x_tile_number, y_tile_number;
- int tile_off, tile_base;
-
- x += irb->region->draw_x;
- y += irb->region->draw_y;
-
- tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
-
- xbyte = x * irb->region->cpp;
-
- x_tile_off = xbyte & 0x7f;
- y_tile_off = y & 0x1f;
-
- x_tile_number = xbyte >> 7;
- y_tile_number = y >> 5;
-
- tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
- (x_tile_off & 0xf);
-
- switch (irb->region->bit_6_swizzle) {
- case I915_BIT_6_SWIZZLE_NONE:
- break;
- case I915_BIT_6_SWIZZLE_9:
- tile_off ^= ((tile_off >> 3) & 64);
- break;
- case I915_BIT_6_SWIZZLE_9_10:
- tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
- break;
- case I915_BIT_6_SWIZZLE_9_11:
- tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
- break;
- case I915_BIT_6_SWIZZLE_9_10_11:
- tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
- ((tile_off >> 5) & 64);
- break;
- default:
- fprintf(stderr, "Unknown tile swizzling mode %d\n",
- irb->region->bit_6_swizzle);
- exit(1);
- }
-
- tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
-
- return tile_base + tile_off;
-}
-
-/*
- break intelWriteRGBASpan_ARGB8888
-*/
-
#undef DBG
#define DBG 0
@@ -280,50 +68,43 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
#define HW_UNLOCK()
-/* Convenience macros to avoid typing the swizzle argument over and over */
-#define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X), (_Y))
-#define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X), (_Y))
-#define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X), (_Y))
+/* Convenience macros to avoid typing the address argument over and over */
+#define NO_TILE(_X, _Y) (((_Y) * irb->region->pitch + (_X)) * irb->region->cpp)
/* r5g6b5 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_RGB
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_RGB565
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+#define TAG(x) intel_##x##_RGB565
+#define TAG2(x,y) intel_##x##y_RGB565
+#include "spantmp2.h"
/* a4r4g4b4 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB4444
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
+#define TAG(x) intel_##x##_ARGB4444
+#define TAG2(x,y) intel_##x##y_ARGB4444
+#include "spantmp2.h"
/* a1r5g5b5 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB1555
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
+#define TAG(x) intel_##x##_ARGB1555
+#define TAG2(x,y) intel_##x##y##_ARGB1555
+#include "spantmp2.h"
/* a8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define INTEL_READ_VALUE(offset) pread_32(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB8888
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+#define TAG(x) intel_##x##_ARGB8888
+#define TAG2(x,y) intel_##x##y##_ARGB8888
+#include "spantmp2.h"
/* x8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGR
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
-#define INTEL_TAG(x) x##_xRGB8888
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGR
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+#define TAG(x) intel_##x##_xRGB8888
+#define TAG2(x,y) intel_##x##y##_xRGB8888
+#include "spantmp2.h"
#define LOCAL_DEPTH_VARS \
struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
@@ -339,18 +120,22 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
/* z16 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLushort
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
-#define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
-#define INTEL_TAG(name) name##_z16
-#include "intel_depthtmp.h"
-
-/* z24x8 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLuint
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
-#define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
-#define INTEL_TAG(name) name##_z24_x8
-#include "intel_depthtmp.h"
+#define VALUE_TYPE GLushort
+#define WRITE_DEPTH(_x, _y, d) \
+ (*(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
+#define READ_DEPTH(d, _x, _y) \
+ d = *(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
+#define TAG(x) intel_##x##_z16
+#include "depthtmp.h"
+
+/* z24_s8 and z24_x8 depthbuffer functions. */
+#define VALUE_TYPE GLuint
+#define WRITE_DEPTH(_x, _y, d) \
+ (*(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
+#define READ_DEPTH(d, _x, _y) \
+ d = *(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
+#define TAG(x) intel_##x##_z24_x8
+#include "depthtmp.h"
void
intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
@@ -360,8 +145,7 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
if (irb == NULL || irb->region == NULL)
return;
- if (intel->intelScreen->kernel_exec_fencing)
- drm_intel_gem_bo_map_gtt(irb->region->buffer);
+ drm_intel_gem_bo_map_gtt(irb->region->buffer);
intel_set_span_functions(intel, rb);
}
@@ -375,10 +159,7 @@ intel_renderbuffer_unmap(struct intel_context *intel,
if (irb == NULL || irb->region == NULL)
return;
- if (intel->intelScreen->kernel_exec_fencing)
- drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
- else
- clear_span_cache(irb);
+ drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
rb->GetRow = NULL;
rb->PutRow = NULL;
@@ -558,158 +339,34 @@ intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb)
{
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
- uint32_t tiling = irb->region->tiling;
-
- if (intel->intelScreen->kernel_exec_fencing) {
- switch (irb->Base.Format) {
- case MESA_FORMAT_RGB565:
- intel_gttmap_InitPointers_RGB565(rb);
- break;
- case MESA_FORMAT_ARGB4444:
- intel_gttmap_InitPointers_ARGB4444(rb);
- break;
- case MESA_FORMAT_ARGB1555:
- intel_gttmap_InitPointers_ARGB1555(rb);
- break;
- case MESA_FORMAT_XRGB8888:
- intel_gttmap_InitPointers_xRGB8888(rb);
- break;
- case MESA_FORMAT_ARGB8888:
- intel_gttmap_InitPointers_ARGB8888(rb);
- break;
- case MESA_FORMAT_Z16:
- intel_gttmap_InitDepthPointers_z16(rb);
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- intel_gttmap_InitDepthPointers_z24_x8(rb);
- break;
- default:
- _mesa_problem(NULL,
- "Unexpected MesaFormat %d in intelSetSpanFunctions",
- irb->Base.Format);
- break;
- }
- return;
- }
- /* If in GEM mode, we need to do the tile address swizzling ourselves,
- * instead of the fence registers handling it.
- */
switch (irb->Base.Format) {
case MESA_FORMAT_RGB565:
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_RGB565(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_RGB565(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_RGB565(rb);
- break;
- }
+ intel_InitPointers_RGB565(rb);
break;
case MESA_FORMAT_ARGB4444:
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_ARGB4444(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_ARGB4444(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_ARGB4444(rb);
- break;
- }
+ intel_InitPointers_ARGB4444(rb);
break;
case MESA_FORMAT_ARGB1555:
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_ARGB1555(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_ARGB1555(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_ARGB1555(rb);
- break;
- }
+ intel_InitPointers_ARGB1555(rb);
break;
case MESA_FORMAT_XRGB8888:
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_xRGB8888(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_xRGB8888(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_xRGB8888(rb);
- break;
- }
+ intel_InitPointers_xRGB8888(rb);
break;
case MESA_FORMAT_ARGB8888:
- /* 8888 RGBA */
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_ARGB8888(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_ARGB8888(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_ARGB8888(rb);
- break;
- }
+ intel_InitPointers_ARGB8888(rb);
break;
case MESA_FORMAT_Z16:
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitDepthPointers_z16(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitDepthPointers_z16(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitDepthPointers_z16(rb);
- break;
- }
+ intel_InitDepthPointers_z16(rb);
break;
case MESA_FORMAT_X8_Z24:
case MESA_FORMAT_S8_Z24:
- /* There are a few different ways SW asks us to access the S8Z24 data:
- * Z24 depth-only depth reads
- * S8Z24 depth reads
- * S8Z24 stencil reads.
- */
- if (rb->Format == MESA_FORMAT_S8_Z24) {
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitDepthPointers_z24_x8(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitDepthPointers_z24_x8(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitDepthPointers_z24_x8(rb);
- break;
- }
- } else {
- _mesa_problem(NULL,
- "Unexpected ActualFormat in intelSetSpanFunctions");
- }
+ intel_InitDepthPointers_z24_x8(rb);
break;
default:
_mesa_problem(NULL,
- "Unexpected MesaFormat in intelSetSpanFunctions");
+ "Unexpected MesaFormat %d in intelSetSpanFunctions",
+ irb->Base.Format);
break;
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_spantmp.h b/src/mesa/drivers/dri/intel/intel_spantmp.h
deleted file mode 100644
index bad03398f6..0000000000
--- a/src/mesa/drivers/dri/intel/intel_spantmp.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Eric Anholt <eric@anholt.net>
- *
- */
-
-/**
- * Wrapper around the spantmp.h macrofest to generate spans code for
- * all the tiling styles.
- */
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define TAG(x) INTEL_TAG(intel_gttmap_##x)
-#define TAG2(x, y) INTEL_TAG(intel_gttmap_##x##y)
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(NO_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel##x)
-#define TAG2(x, y) INTEL_TAG(intel##x)##y
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(X_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(X_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_XTile_##x)
-#define TAG2(x, y) INTEL_TAG(intel_XTile_##x)##y
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(Y_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(Y_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_YTile_##x)
-#define TAG2(x, y) INTEL_TAG(intel_YTile_##x)##y
-#include "spantmp2.h"
-
-#undef INTEL_PIXEL_FMT
-#undef INTEL_PIXEL_TYPE
-#undef INTEL_WRITE_VALUE
-#undef INTEL_READ_VALUE
-#undef INTEL_TAG