[965] Move to using shared texture management code.

This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support.  It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.

4 files changed, 37 insertions, 20 deletions

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index df7b3d378c..4d36fc0025 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -78,28 +78,17 @@ intel_miptree_create(struct intel_context *intel,
    mt->compressed = compress_byte ? 1 : 0;
    mt->refcount = 1; 
 
-   switch (intel->intelScreen->deviceID) {
-   case PCI_CHIP_I945_G:
-   case PCI_CHIP_I945_GM:
-   case PCI_CHIP_I945_GME:
-   case PCI_CHIP_G33_G:
-   case PCI_CHIP_Q33_G:
-   case PCI_CHIP_Q35_G:
+#ifdef I915
+   if (IS_945(intel->intelScreen->deviceID))
       ok = i945_miptree_layout(mt);
-      break;
-   case PCI_CHIP_I915_G:
-   case PCI_CHIP_I915_GM:
-   case PCI_CHIP_I830_M:
-   case PCI_CHIP_I855_GM:
-   case PCI_CHIP_I865_G:
-   default:
-      /* All the i830 chips and the i915 use this layout:
-       */
+   else
       ok = i915_miptree_layout(mt);
-      break;
-   }
+#else
+   ok = brw_miptree_layout(mt);
+#endif
 
    if (ok) {
+#ifdef I915
       if (!mt->compressed) {
 	 int align;
 
@@ -125,6 +114,7 @@ intel_miptree_create(struct intel_context *intel,
 
 	 mt->pitch /= cpp;
       }
+#endif /* I915 */
 
       mt->region = intel_region_alloc(intel,
                                       mt->cpp, mt->pitch, mt->total_height);
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index ecdb7be244..4a76717688 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -192,7 +192,6 @@ void intel_miptree_image_copy(struct intel_context *intel,
  */
 GLboolean i915_miptree_layout(struct intel_mipmap_tree *mt);
 GLboolean i945_miptree_layout(struct intel_mipmap_tree *mt);
-
-
+GLboolean brw_miptree_layout(struct intel_mipmap_tree *mt);
 
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_tex.c b/src/mesa/drivers/dri/intel/intel_tex.c
index b08dee43bc..e02972ec63 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.c
+++ b/src/mesa/drivers/dri/intel/intel_tex.c
@@ -1,3 +1,4 @@
+#include "swrast/swrast.h"
 #include "texobj.h"
 #include "intel_context.h"
 #include "intel_mipmap_tree.h"
@@ -166,10 +167,17 @@ intelInitTextureFuncs(struct dd_function_table *functions)
    functions->TexSubImage1D = intelTexSubImage1D;
    functions->TexSubImage2D = intelTexSubImage2D;
    functions->TexSubImage3D = intelTexSubImage3D;
+#ifdef I915
    functions->CopyTexImage1D = intelCopyTexImage1D;
    functions->CopyTexImage2D = intelCopyTexImage2D;
    functions->CopyTexSubImage1D = intelCopyTexSubImage1D;
    functions->CopyTexSubImage2D = intelCopyTexSubImage2D;
+#else
+   functions->CopyTexImage1D = _swrast_copy_teximage1d;
+   functions->CopyTexImage2D = _swrast_copy_teximage2d;
+   functions->CopyTexSubImage1D = _swrast_copy_texsubimage1d;
+   functions->CopyTexSubImage2D = _swrast_copy_texsubimage2d;
+#endif
    functions->GetTexImage = intelGetTexImage;
 
    /* compressed texture functions */
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index af18c26d55..8df66ad445 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -40,6 +40,7 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj)
          firstLevel = lastLevel = tObj->BaseLevel;
       }
       else {
+#ifdef I915
          firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5);
          firstLevel = MAX2(firstLevel, tObj->BaseLevel);
          lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5);
@@ -47,6 +48,18 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj)
          lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
          lastLevel = MIN2(lastLevel, tObj->MaxLevel);
          lastLevel = MAX2(firstLevel, lastLevel);       /* need at least one level */
+#else
+	 /* Currently not taking min/max lod into account here, those
+	  * values are programmed as sampler state elsewhere and we
+	  * upload the same mipmap levels regardless.  Not sure if
+	  * this makes sense as it means it isn't possible for the app
+	  * to use min/max lod to reduce texture memory pressure:
+	  */
+	 firstLevel = tObj->BaseLevel;
+	 lastLevel = MIN2(tObj->BaseLevel + baseImage->MaxLog2,
+			  tObj->MaxLevel);
+	 lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
+#endif
       }
       break;
    case GL_TEXTURE_RECTANGLE_NV:
@@ -211,8 +224,15 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
       }
    }
 
+#ifdef I915
+   /* XXX: what is this flush about?
+    * On 965, it causes a batch flush in the middle of the state relocation
+    * emits, which means that the eventual rendering doesn't have all of the
+    * required relocations in place.
+    */
    if (need_flush)
       intel_batchbuffer_flush(intel->batch);
+#endif
 
    return GL_TRUE;
 }