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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-09-30 10:49:47 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2010-09-30 10:51:26 +0800
commit72b368ae69bc037681ab4e458296c07cb04349be (patch)
treec490c5be2f6d56bbaf3509bacb507a215eac78bc /src/mesa/drivers/dri/intel
parent83278d384ee123fa207229cc444f6e77e2d9a0d2 (diff)
i965: always set tiling for fbo depth buffer on sandybridge
Sandybridge requires depth buffer must be tiling. Fix 'fbo_firecube' demo.
Diffstat (limited to 'src/mesa/drivers/dri/intel')
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 984585027c..8c0491d59a 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -102,7 +102,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
{
struct intel_context *intel = intel_context(ctx);
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- int cpp;
+ int cpp, tiling;
ASSERT(rb->Name != 0);
@@ -176,7 +176,13 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
/* alloc hardware renderbuffer */
DBG("Allocating %d x %d Intel RBO\n", width, height);
- irb->region = intel_region_alloc(intel->intelScreen, I915_TILING_NONE, cpp,
+ tiling = I915_TILING_NONE;
+
+ /* Gen6 requires depth must be tiling */
+ if (intel->gen >= 6 && rb->Format == MESA_FORMAT_S8_Z24)
+ tiling = I915_TILING_Y;
+
+ irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
width, height, GL_TRUE);
if (!irb->region)
return GL_FALSE; /* out of memory? */