diff options
author | Eric Anholt <anholt@FreeBSD.org> | 2005-11-02 01:15:07 +0000 |
---|---|---|
committer | Eric Anholt <anholt@FreeBSD.org> | 2005-11-02 01:15:07 +0000 |
commit | 3a5626cb846ad767fe1c38fe35ebe4df3e3a0454 (patch) | |
tree | ea04046515c2f8c69e413416fe4baca8d1b66163 /src/mesa/drivers/dri/r200/r200_state_init.c | |
parent | a9b927cb6e5b4a98cf324faa2b0d61de1ce1a090 (diff) |
First step of Radeon DRI unification:
- Makes all three drivers use the same screen structure and setup code, with a
few ifdefs for the separate compilation to deal with symbols not being
available to all drivers and the fact that we have no mechanism for dealing
with different config options for different chip families in the same driver.
These issues should be dealt with later.
- Introduces IS_R[123]00_CLASS(radeonScreenPtr) macro for code for taking
different paths depending on the general class of chipset.
- Adds many new R300-class PCI IDs, though not all those listed in
radeon_driver.c.
Diffstat (limited to 'src/mesa/drivers/dri/r200/r200_state_init.c')
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_state_init.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index ead80d2c32..24fe43a8f5 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -253,7 +253,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); if (rmesa->r200Screen->drmSupportsFragShader) { - if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) { + if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) { /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); @@ -273,7 +273,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } else { - if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) { + if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) { ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); @@ -536,7 +536,7 @@ void r200InitState( r200ContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | R200_Z_DECOMPRESSION_ENABLE; -/* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) +/* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ } @@ -640,7 +640,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_VC_NO_SWAP; #endif - if (!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) { + if (!(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) { /* Bypass TCL */ rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); } |