diff options
| author | Roland Scheidegger <rscheidegger@gmx.ch> | 2004-12-08 17:32:46 +0000 |
|---|---|---|
| committer | Roland Scheidegger <rscheidegger@gmx.ch> | 2004-12-08 17:32:46 +0000 |
| commit | b31b7836d6e7abf80dd4feacce333d4b1fe6e4ab (patch) | |
| tree | 69a6cac0c72bb720919cf727bcb53d40d6920c13 /src/mesa/drivers/dri/r200/r200_state_init.c | |
| parent | fc236723273d4d872ae5e7cac876ea20175df10d (diff) | |
(Stephane Marchesin, me) add hyperz support to radeon and r200 drivers. Only fast z clear and z buffer compression are supported for now, hierarchical-z is not. Still problems with multiple apps and z/stencil readback, which is why hyperz is disabled per default. Also add the new point sprite packet drm 1.13 accepts to the sanity code.
Diffstat (limited to 'src/mesa/drivers/dri/r200/r200_state_init.c')
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_state_init.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 610706bd31..5d36a6823a 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -169,14 +169,16 @@ void r200InitState( r200ContextPtr rmesa ) switch ( ctx->Visual.depthBits ) { case 16: + rmesa->state.depth.clear = 0x0000ffff; rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z; rmesa->state.stencil.clear = 0x00000000; break; case 24: + rmesa->state.depth.clear = 0x00ffffff; rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; - rmesa->state.stencil.clear = 0xff000000; + rmesa->state.stencil.clear = 0xffff0000; break; default: fprintf( stderr, "Error: Unsupported depth %d... exiting\n", @@ -448,15 +450,25 @@ void r200InitState( r200ContextPtr rmesa ) ((rmesa->r200Screen->depthPitch & R200_DEPTHPITCH_MASK) | R200_DEPTH_ENDIAN_NO_SWAP); + + if (rmesa->using_hyperz) + rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | - R200_Z_TEST_LESS | + R200_Z_TEST_LESS | R200_STENCIL_TEST_ALWAYS | R200_STENCIL_FAIL_KEEP | R200_STENCIL_ZPASS_KEEP | R200_STENCIL_ZFAIL_KEEP | R200_Z_WRITE_ENABLE); + if (rmesa->using_hyperz) { + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | + R200_Z_DECOMPRESSION_ENABLE; +/* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ + } + rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE | R200_TEX_BLEND_0_ENABLE); |