radeon/r200/r300: fix up the whole buffer space checking.

This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.

This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state

1 files changed, 15 insertions, 33 deletions

diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index ca4dee8a5b..f040713980 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -2273,33 +2273,24 @@ static void update_texturematrix( GLcontext *ctx )
 static GLboolean r200ValidateBuffers(GLcontext *ctx)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   struct radeon_cs_space_check bos[8];
    struct radeon_renderbuffer *rrb;
-   int num_bo = 0;
    int i;
-   int flushed = 0, ret;
-again:
-   num_bo = 0;
+
+   radeon_validate_reset_bos(&rmesa->radeon);
    
    rrb = radeon_get_colorbuffer(&rmesa->radeon);
    /* color buffer */
    if (rrb && rrb->bo) {
-      bos[num_bo].bo = rrb->bo;
-      bos[num_bo].read_domains = 0;
-      bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
-      bos[num_bo].new_accounted = 0;
-      num_bo++;
+     radeon_validate_bo(&rmesa->radeon, rrb->bo,
+			0, RADEON_GEM_DOMAIN_VRAM);
    }
 
    /* depth buffer */
    rrb = radeon_get_depthbuffer(&rmesa->radeon);
    /* color buffer */
    if (rrb && rrb->bo) {
-      bos[num_bo].bo = rrb->bo;
-      bos[num_bo].read_domains = 0;
-      bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
-      bos[num_bo].new_accounted = 0;
-      num_bo++;
+     radeon_validate_bo(&rmesa->radeon, rrb->bo,
+			0, RADEON_GEM_DOMAIN_VRAM);
    }
 
    for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
@@ -2307,26 +2298,17 @@ again:
       
       if (!ctx->Texture.Unit[i]._ReallyEnabled)
 	 continue;
-      
+
       t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
-      bos[num_bo].bo = t->mt->bo;
-      bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
-      bos[num_bo].write_domain = 0;
-      bos[num_bo].new_accounted = 0;
-      num_bo++;
+      if (t->image_override && t->bo)
+	radeon_validate_bo(&rmesa->radeon, t->bo,
+			   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+      else if (t->mt->bo)
+	radeon_validate_bo(&rmesa->radeon, t->mt->bo,
+			   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
    }
-   
-   ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo);
-   if (ret == RADEON_CS_SPACE_OP_TO_BIG)
-      return GL_FALSE;
-   if (ret == RADEON_CS_SPACE_FLUSH) {
-      radeonFlush(ctx);
-      if (flushed)
-	 return GL_FALSE;
-      flushed = 1;
-      goto again;
-   }
-   return GL_TRUE;
+
+   return radeon_revalidate_bos(ctx);
 }
 
 GLboolean r200ValidateState( GLcontext *ctx )