diff options
| author | Oliver McFadden <z3ro.geek@gmail.com> | 2008-02-29 05:01:02 +0000 |
|---|---|---|
| committer | Oliver McFadden <z3ro.geek@gmail.com> | 2008-03-01 06:33:07 +0000 |
| commit | 3129d8b512d50335fc5c219b65e36fcaaffcd247 (patch) | |
| tree | 7541a4b761094cac9a1e612be50868d4c36efb57 /src/mesa/drivers/dri/r300/r300_vertprog.h | |
| parent | 9a3d4b14e968c1203b58d782f7ad60bfb61150d9 (diff) | |
r300: Added the PVS_OP_DST_OPERAND documentation from AMD.
Diffstat (limited to 'src/mesa/drivers/dri/r300/r300_vertprog.h')
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_vertprog.h | 39 |
1 files changed, 17 insertions, 22 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.h b/src/mesa/drivers/dri/r300/r300_vertprog.h index 5727449bc0..61da603371 100644 --- a/src/mesa/drivers/dri/r300/r300_vertprog.h +++ b/src/mesa/drivers/dri/r300/r300_vertprog.h @@ -3,17 +3,6 @@ #include "r300_reg.h" -/* TODO: get documentation from AMD for these... */ - -#define R300_VPI_OUT_REG_INDEX_SHIFT 13 - /* GUESS based on fglrx native limits */ -#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) - -#define R300_VPI_OUT_WRITE_X (1 << 20) -#define R300_VPI_OUT_WRITE_Y (1 << 21) -#define R300_VPI_OUT_WRITE_Z (1 << 22) -#define R300_VPI_OUT_WRITE_W (1 << 23) - #define R300_VPI_IN_REG_INDEX_SHIFT 5 /* GUESS based on fglrx native limits */ #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) @@ -29,17 +18,18 @@ #define R300_VPI_IN_NEG_W (1 << 28) #define PVS_VECTOR_OPCODE(opcode, reg_index, reg_writemask, reg_class) \ - ((opcode) \ - | ((reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT) \ - | ((reg_writemask) << 20) \ - | ((reg_class) << 8)) + (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \ + | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \ + | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \ + | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT)) #define PVS_MATH_OPCODE(opcode, reg_index, reg_writemask, reg_class) \ - ((opcode) \ - | (1 << 6) /* FIXME: PVS_DST_MATH_INST */ \ - | ((reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT) \ - | ((reg_writemask) << 20) \ - | ((reg_class) << 8)) + (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \ + | ((1 & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT) \ + | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \ + | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \ + | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT)) + #define PVS_SOURCE_OPCODE(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \ (((in_reg_index) << R300_VPI_IN_REG_INDEX_SHIFT) \ @@ -60,6 +50,11 @@ #define VSF_FLAG_ALL 0xf #define VSF_FLAG_NONE 0 +#define R300_VPI_OUT_WRITE_X (1 << 20) +#define R300_VPI_OUT_WRITE_Y (1 << 21) +#define R300_VPI_OUT_WRITE_Z (1 << 22) +#define R300_VPI_OUT_WRITE_W (1 << 23) + #define VP_OUTMASK_X R300_VPI_OUT_WRITE_X #define VP_OUTMASK_Y R300_VPI_OUT_WRITE_Y #define VP_OUTMASK_Z R300_VPI_OUT_WRITE_Z @@ -78,8 +73,8 @@ #define VP_OUT(instr,outclass,outidx,outmask) \ (VE_##instr | \ - ((outidx) << R300_VPI_OUT_REG_INDEX_SHIFT) | \ - (PVS_DST_REG_##outclass << 8) | \ + ((outidx & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) | \ + ((PVS_DST_REG_##outclass & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT) | \ VP_OUTMASK_##outmask) #define VP_IN(inclass,inidx) \ |