radeon: remove start/end offset + cleanup some whitespace

4 files changed, 33 insertions, 42 deletions

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index ed94520aba..4eac5183b2 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -341,14 +341,14 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
 			} else if (!t) {
 				OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 			} else {
-                if (t->bo) {
-                    OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
-                    RADEON_GEM_DOMAIN_VRAM, 0, 0);
-                } else {
-    				OUT_BATCH(t->override_offset);
-                }
+				if (t->bo) {
+					OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
+							RADEON_GEM_DOMAIN_VRAM, 0, 0);
+				} else {
+					OUT_BATCH(t->override_offset);
+				}
 			}
-            END_BATCH();
+			END_BATCH();
 		}
 	}
 }
@@ -361,9 +361,9 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
 	GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate;
 
 	rrb = r300->radeon.state.color.rrb;
-    if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
-        rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-    }
+	if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+		rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+	}
 	if (!rrb || !rrb->bo) {
 		fprintf(stderr, "no rrb\n");
 		return;
@@ -397,13 +397,13 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
 		return;
 
 	zbpitch = (rrb->pitch / rrb->cpp);
-    if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
-        zbpitch |= R300_DEPTHMACROTILE_ENABLE;
-    }
-    if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
-        zbpitch |= R300_DEPTHMICROTILE_TILED;
-    }
-
+	if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+		zbpitch |= R300_DEPTHMACROTILE_ENABLE;
+	}
+	if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
+		zbpitch |= R300_DEPTHMICROTILE_TILED;
+	}
+	
 	BEGIN_BATCH(4);
 	OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 	OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
@@ -688,43 +688,43 @@ void r300InitCmdBuf(r300ContextPtr r300)
 		ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 		r300->hw.vpi.cmd[0] =
 		    cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
-    	r300->hw.vpi.emit = emit_vpu;
+		r300->hw.vpi.emit = emit_vpu;
 
 		if (is_r500) {
 		    ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 		    r300->hw.vpp.cmd[0] =
 			cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
-        	r300->hw.vpp.emit = emit_vpu;
+		    r300->hw.vpp.emit = emit_vpu;
 
 		    ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 		    r300->hw.vps.cmd[0] =
 			cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
-        	r300->hw.vps.emit = emit_vpu;
+		    r300->hw.vps.emit = emit_vpu;
 
 			for (i = 0; i < 6; i++) {
-				ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
-				r300->hw.vpucp[i].cmd[0] =
-					cmdvpu(r300->radeon.radeonScreen,
+			  ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
+			  r300->hw.vpucp[i].cmd[0] =
+				  cmdvpu(r300->radeon.radeonScreen,
                            R500_PVS_UCP_START + i, 1);
-              	r300->hw.vpucp[i].emit = emit_vpu;
+				r300->hw.vpucp[i].emit = emit_vpu;
 			}
 		} else {
 		    ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 		    r300->hw.vpp.cmd[0] =
 			cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
-            r300->hw.vpp.emit = emit_vpu;
+		    r300->hw.vpp.emit = emit_vpu;
 
 		    ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 		    r300->hw.vps.cmd[0] =
 			cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
-            r300->hw.vps.emit = emit_vpu;
+		    r300->hw.vps.emit = emit_vpu;
 
 			for (i = 0; i < 6; i++) {
 				ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 				r300->hw.vpucp[i].cmd[0] =
 					cmdvpu(r300->radeon.radeonScreen,
-                           R300_PVS_UCP_START + i, 1);
-                r300->hw.vpucp[i].emit = emit_vpu;
+					       R300_PVS_UCP_START + i, 1);
+				r300->hw.vpucp[i].emit = emit_vpu;
 			}
 		}
 	}
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index 95701b49b4..bb7e0bf296 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -93,8 +93,6 @@ void r300BeginBatch(r300ContextPtr r300,
         radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\
         radeon_cs_write_reloc(b_l_r300->cmdbuf.cs, \
                               bo, \
-                              offset, \
-                              (bo)->size, \
                               rd, \
                               wd, \
                               flags);\
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 0cf084bde5..6d7b191b24 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -499,9 +499,9 @@ static void r300EmitClearState(GLcontext * ctx)
 		OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
 		END_BATCH();
 
-        vpu.check = check_vpu;
-        vpu.cmd = _cmd;
-        vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
+		vpu.check = check_vpu;
+		vpu.cmd = _cmd;
+		vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
 
 		vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
                                          0, 0xf, PVS_DST_REG_OUT);
@@ -520,6 +520,7 @@ static void r300EmitClearState(GLcontext * ctx)
 		vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
                                       PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
                                       PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
+
                                       VSF_FLAG_NONE);
 		vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
                                       PVS_SRC_SELECT_FORCE_0,
@@ -527,7 +528,7 @@ static void r300EmitClearState(GLcontext * ctx)
                                       PVS_SRC_SELECT_FORCE_0,
                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 		vpu.cmd[8] = 0x0;
-        emit_vpu(r300, &vpu);
+		emit_vpu(r300, &vpu);
 	}
 }
 
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index dd9da80fd0..ccc00b381f 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -214,8 +214,6 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
         OUT_BATCH(vertex_count);
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.elt_dma_bo,
-                              0,
-                              rmesa->state.elt_dma_bo->size,
                               RADEON_GEM_DOMAIN_GTT, 0, 0);
     }
     	END_BATCH();
@@ -299,16 +297,12 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
                    offset * 4 * rmesa->state.aos[i + 0].stride;
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.aos[i+0].bo,
-                              voffset,
-                              rmesa->state.aos[i+0].bo->size,
                               RADEON_GEM_DOMAIN_GTT,
                               0, 0);
         voffset =  rmesa->state.aos[i + 1].offset +
                    offset * 4 * rmesa->state.aos[i + 1].stride;
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.aos[i+1].bo,
-                              voffset,
-                              rmesa->state.aos[i+1].bo->size,
                               RADEON_GEM_DOMAIN_GTT,
                               0, 0);
 	}
@@ -317,8 +311,6 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
                    offset * 4 * rmesa->state.aos[nr - 1].stride;
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.aos[nr-1].bo,
-                              voffset,
-                              rmesa->state.aos[nr-1].bo->size,
                               RADEON_GEM_DOMAIN_GTT,
                               0, 0);
 	}