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authorDave Airlie <airlied@itt42.(none)>2009-11-20 11:48:10 +1000
committerDave Airlie <airlied@itt42.(none)>2009-11-20 11:48:10 +1000
commit3f2c77659ca552c43f544228f3a5a5fe6365513a (patch)
treef98f22ac8a1dbcaa9c457d8f64731c6d4a374cdb /src/mesa/drivers/dri/r600/r600_tex.c
parentb09e74901a4f92299fe3f52f57d27fd5ca5bdd2d (diff)
parentf8ea5318200c1ed839fc387b16a57c8d9969974b (diff)
Merge remote branch 'origin/mesa_7_7_branch'
Diffstat (limited to 'src/mesa/drivers/dri/r600/r600_tex.c')
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.c17
1 files changed, 3 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 20965bb3c8..9d83a64e22 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -312,16 +312,7 @@ static void r600TexParameter(GLcontext * ctx, GLenum target,
case GL_TEXTURE_MAX_LEVEL:
case GL_TEXTURE_MIN_LOD:
case GL_TEXTURE_MAX_LOD:
- /* This isn't the most efficient solution but there doesn't appear to
- * be a nice alternative. Since there's no LOD clamping,
- * we just have to rely on loading the right subset of mipmap levels
- * to simulate a clamped LOD.
- */
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = 0;
- t->validated = GL_FALSE;
- }
+ t->validated = GL_FALSE;
break;
case GL_DEPTH_TEXTURE_MODE:
@@ -369,10 +360,8 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
t->bo = NULL;
}
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = 0;
- }
+ radeon_miptree_unreference(&t->mt);
+
_mesa_delete_texture_object(ctx, texObj);
}