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authorAndre Maasikas <amaasikas@gmail.com>2009-12-22 14:50:10 +0200
committerAndre Maasikas <amaasikas@gmail.com>2010-01-05 15:36:32 +0200
commitc91ceeec320daebe7d9d78ed2d80a2265bcfa8c2 (patch)
tree44432bd04e060d22fa31f3c89a340d7206f9c4d9 /src/mesa/drivers/dri/r600/r700_chip.c
parent750c1e7bb4b5caab699d8bce8906b5ca138eac51 (diff)
r600: adjust after radeon mipmap changes in 7118db8700
R600_OUT_BATCH_RELOC doesn't really use offset so set it in TEX_RESOURCE2 + typo fix
Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_chip.c')
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index c124e02184..3bc2d2ba02 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -57,14 +57,11 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
radeonTexObj *t = r700->textures[i];
- uint32_t offset;
if (t) {
if (!t->image_override) {
bo = t->mt->bo;
- offset = get_base_teximage_offset(t);
} else {
bo = t->bo;
- offset = 0;
}
if (bo) {
@@ -93,7 +90,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
bo,
- offset,
+ r700->textures[i]->SQ_TEX_RESOURCE2,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
bo,