diff options
author | José Fonseca <jfonseca@vmware.com> | 2010-01-08 15:42:57 +0000 |
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committer | José Fonseca <jfonseca@vmware.com> | 2010-01-08 15:42:57 +0000 |
commit | 080c40ab32b2abd6d8381b4a0cc143d36a1652b2 (patch) | |
tree | e173767ebc5a82d81b9fc086449d915e29348976 /src/mesa/drivers/dri/radeon/radeon_queryobj.c | |
parent | 9cdf6f025b2ed55cfb13dd09f870f01d0c7947d3 (diff) | |
parent | a1de400e8de06a80ab140bb0fa950e990607572d (diff) |
Merge remote branch 'origin/master' into lp-binning
Conflicts:
src/gallium/auxiliary/util/u_surface.c
src/gallium/drivers/llvmpipe/Makefile
src/gallium/drivers/llvmpipe/SConscript
src/gallium/drivers/llvmpipe/lp_bld_arit.c
src/gallium/drivers/llvmpipe/lp_bld_flow.c
src/gallium/drivers/llvmpipe/lp_bld_interp.c
src/gallium/drivers/llvmpipe/lp_clear.c
src/gallium/drivers/llvmpipe/lp_context.c
src/gallium/drivers/llvmpipe/lp_context.h
src/gallium/drivers/llvmpipe/lp_draw_arrays.c
src/gallium/drivers/llvmpipe/lp_jit.c
src/gallium/drivers/llvmpipe/lp_jit.h
src/gallium/drivers/llvmpipe/lp_prim_vbuf.c
src/gallium/drivers/llvmpipe/lp_setup.c
src/gallium/drivers/llvmpipe/lp_setup_point.c
src/gallium/drivers/llvmpipe/lp_state.h
src/gallium/drivers/llvmpipe/lp_state_blend.c
src/gallium/drivers/llvmpipe/lp_state_derived.c
src/gallium/drivers/llvmpipe/lp_state_fs.c
src/gallium/drivers/llvmpipe/lp_state_sampler.c
src/gallium/drivers/llvmpipe/lp_state_surface.c
src/gallium/drivers/llvmpipe/lp_tex_cache.c
src/gallium/drivers/llvmpipe/lp_tex_cache.h
src/gallium/drivers/llvmpipe/lp_tex_sample.h
src/gallium/drivers/llvmpipe/lp_tile_cache.c
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_queryobj.c')
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_queryobj.c | 56 |
1 files changed, 32 insertions, 24 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c index b79d864ba2..98117cdfc1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c @@ -31,24 +31,11 @@ #include "main/imports.h" #include "main/simple_list.h" -static int radeonQueryIsFlushed(GLcontext *ctx, struct gl_query_object *q) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - struct radeon_query_object *tmp, *query = (struct radeon_query_object *)q; - - foreach(tmp, &radeon->query.not_flushed_head) { - if (tmp == query) { - return 0; - } - } - - return 1; -} - static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = (struct radeon_query_object *)q; - uint32_t *result; + uint32_t *result; int i; radeon_print(RADEON_STATE, RADEON_VERBOSE, @@ -56,13 +43,35 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) __FUNCTION__, query->Base.Id, (int) query->Base.Result); radeon_bo_map(query->bo, GL_FALSE); - - result = query->bo->ptr; + result = query->bo->ptr; query->Base.Result = 0; - for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) { - query->Base.Result += result[i]; - radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, result[i]); + if (IS_R600_CLASS(radeon->radeonScreen)) { + /* ZPASS EVENT writes alternating qwords + * At query start we set the start offset to 0 and + * hw writes zpass start counts to qwords 0, 2, 4, 6. + * At query end we set the start offset to 8 and + * hw writes zpass end counts to qwords 1, 3, 5, 7. + * then we substract. MSB is the valid bit. + */ + for (i = 0; i < 16; i += 4) { + uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) | + (uint64_t)LE32_TO_CPU(result[i + 1]) << 32; + uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) | + (uint64_t)LE32_TO_CPU(result[i + 3]) << 32; + if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) { + uint64_t query_count = end - start; + query->Base.Result += query_count; + + } + radeon_print(RADEON_STATE, RADEON_TRACE, + "%d start: %lx, end: %lx %ld\n", i, start, end, end - start); + } + } else { + for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) { + query->Base.Result += LE32_TO_CPU(result[i]); + radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i])); + } } radeon_bo_unmap(query->bo); @@ -99,10 +108,11 @@ static void radeonDeleteQuery(GLcontext *ctx, struct gl_query_object *q) static void radeonWaitQuery(GLcontext *ctx, struct gl_query_object *q) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = (struct radeon_query_object *)q; /* If the cmdbuf with packets for this query hasn't been flushed yet, do it now */ - if (!radeonQueryIsFlushed(ctx, q)) + if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) ctx->Driver.Flush(ctx); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s: query id %d, bo %p, offset %d\n", __FUNCTION__, q->Id, query->bo, query->curr_offset); @@ -134,8 +144,6 @@ static void radeonBeginQuery(GLcontext *ctx, struct gl_query_object *q) radeon->query.queryobj.dirty = GL_TRUE; radeon->hw.is_dirty = GL_TRUE; - insert_at_tail(&radeon->query.not_flushed_head, query); - } void radeonEmitQueryEnd(GLcontext *ctx) @@ -183,7 +191,7 @@ static void radeonCheckQuery(GLcontext *ctx, struct gl_query_object *q) uint32_t domain; /* Need to perform a flush, as per ARB_occlusion_query spec */ - if (!radeonQueryIsFlushed(ctx, q)) { + if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) { ctx->Driver.Flush(ctx); } |