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authorBrian Paul <brian.paul@tungstengraphics.com>2005-09-01 03:54:34 +0000
committerBrian Paul <brian.paul@tungstengraphics.com>2005-09-01 03:54:34 +0000
commit982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9 (patch)
treef367c54ff9697263e3a94847eb4bb952c7dc532b /src/mesa/drivers/dri/radeon/radeon_span.c
parent8e5479c7f806ffd57eed26c147e3ca227a39f0a7 (diff)
Finish up some of the gl_renderbuffer work.
Use driRenderbuffer's offset, pitch fields in the span routines. Remove the SetBuffer driver function. Consolidate the code for setting CTX_RB3D_COLOROFFSET and CTX_RB3D_COLORPITCH state in new radeonUpdateDrawBuffer() function.
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_span.c')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_span.c141
1 files changed, 54 insertions, 87 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 2d15078d6d..dcb7af31ec 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -45,44 +45,47 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_span.h"
#include "radeon_tex.h"
+#include "drirenderbuffer.h"
+
+
#define DBG 0
+#define GET_PTR(X,Y) (sPriv->pFB + drb->flippedOffset \
+ + ((dPriv->y + (Y)) * drb->flippedPitch + (dPriv->x + (X))) * drb->cpp)
+
+/*
+ * Eventually, try to remove all references to ctx/rmesa here.
+ * The renderbuffer parameter to the span functions should provide all
+ * the info needed to read/write the pixels.
+ * We'll be a step closer to supporting Pbuffer and framebuffer objects then.
+ */
#define LOCAL_VARS \
radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- radeonScreenPtr radeonScreen = rmesa->radeonScreen; \
__DRIscreenPrivate *sPriv = rmesa->dri.screen; \
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
- GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp; \
+ driRenderbuffer *drb = (driRenderbuffer *) rb; \
GLuint height = dPriv->h; \
- char *buf = (char *)(sPriv->pFB + \
- rmesa->state.color.drawOffset + \
- (dPriv->x * radeonScreen->cpp) + \
- (dPriv->y * pitch)); \
- char *read_buf = (char *)(sPriv->pFB + \
- rmesa->state.pixel.readOffset + \
- (dPriv->x * radeonScreen->cpp) + \
- (dPriv->y * pitch)); \
GLuint p; \
- (void) read_buf; (void) buf; (void) p
+ (void) p;
#define LOCAL_DEPTH_VARS \
radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- radeonScreenPtr radeonScreen = rmesa->radeonScreen; \
__DRIscreenPrivate *sPriv = rmesa->dri.screen; \
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
+ driRenderbuffer *drb = (driRenderbuffer *) rb; \
GLuint height = dPriv->h; \
GLuint xo = dPriv->x; \
GLuint yo = dPriv->y; \
- char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset); \
- (void) buf
+ char *buf = (char *)(sPriv->pFB + drb->offset);
+
#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
#define Y_FLIP( _y ) (height - _y - 1)
-#define HW_LOCK()
+#define HW_LOCK()
-#define HW_UNLOCK()
+#define HW_UNLOCK()
@@ -97,8 +100,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define TAG(x) radeon##x##_RGB565
#define TAG2(x,y) radeon##x##_RGB565##y
+#define GET_SRC_PTR(X,Y) GET_PTR(X, Y)
+#define GET_DST_PTR(X,Y) GET_PTR(X, Y)
#include "spantmp2.h"
+
/* 32 bit, ARGB8888 color spanline and pixel functions
*/
#define SPANTMP_PIXEL_FMT GL_BGRA
@@ -106,6 +112,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define TAG(x) radeon##x##_ARGB8888
#define TAG2(x,y) radeon##x##_ARGB8888##y
+#define GET_SRC_PTR(X,Y) GET_PTR(X, Y)
+#define GET_DST_PTR(X,Y) GET_PTR(X, Y)
#include "spantmp2.h"
@@ -119,28 +127,29 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* is calculated, and then wired with x and y to produce the final
* memory address.
* The chip will do address translation on its own if the surface registers
- * are set up correctly. It is not quite enough to get it working with hyperz too...
+ * are set up correctly. It is not quite enough to get it working with hyperz
+ * too...
*/
-static GLuint radeon_mba_z32( radeonContextPtr rmesa,
- GLint x, GLint y )
+static GLuint
+radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
{
- GLuint pitch = rmesa->radeonScreen->frontPitch;
- if (rmesa->radeonScreen->depthHasSurface) {
- return 4*(x + y*pitch);
+ GLuint pitch = drb->pitch;
+ if (drb->depthHasSurface) {
+ return 4 * (x + y * pitch);
}
else {
GLuint ba, address = 0; /* a[0..1] = 0 */
ba = (y / 16) * (pitch / 16) + (x / 16);
- address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
- address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
+ address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
+ address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
address |=
(((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
+ address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
+ address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |=
(((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
@@ -149,23 +158,25 @@ static GLuint radeon_mba_z32( radeonContextPtr rmesa,
}
}
-static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y )
+
+static INLINE GLuint
+radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
{
- GLuint pitch = rmesa->radeonScreen->frontPitch;
- if (rmesa->radeonScreen->depthHasSurface) {
- return 2*(x + y*pitch);
+ GLuint pitch = drb->pitch;
+ if (drb->depthHasSurface) {
+ return 2 * (x + y * pitch);
}
else {
GLuint ba, address = 0; /* a[0] = 0 */
ba = (y / 16) * (pitch / 32) + (x / 32);
- address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
- address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
- address |= (x & 0x8) << 4; /* a[7] = x[3] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
+ address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
+ address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
+ address |= (x & 0x8) << 4; /* a[7] = x[3] */
+ address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
+ address |= (y & 0x8) << 7; /* a[10] = y[3] */
+ address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
return address;
@@ -176,19 +187,20 @@ static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y
/* 16-bit depth buffer functions
*/
#define WRITE_DEPTH( _x, _y, d ) \
- *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo )) = d;
+ *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo ));
+ d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
#define TAG(x) radeon##x##_16
#include "depthtmp.h"
+
/* 24 bit depth, 8 bit stencil depthbuffer functions
*/
#define WRITE_DEPTH( _x, _y, d ) \
do { \
- GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
+ GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
GLuint tmp = *(GLuint *)(buf + offset); \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
@@ -196,7 +208,7 @@ do { \
} while (0)
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLuint *)(buf + radeon_mba_z32( rmesa, _x + xo, \
+ d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
_y + yo )) & 0x00ffffff;
#define TAG(x) radeon##x##_24_8
@@ -211,7 +223,7 @@ do { \
*/
#define WRITE_STENCIL( _x, _y, d ) \
do { \
- GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
+ GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
GLuint tmp = *(GLuint *)(buf + offset); \
tmp &= 0x00ffffff; \
tmp |= (((d) & 0xff) << 24); \
@@ -220,7 +232,7 @@ do { \
#define READ_STENCIL( d, _x, _y ) \
do { \
- GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
+ GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
GLuint tmp = *(GLuint *)(buf + offset); \
tmp &= 0xff000000; \
d = tmp >> 24; \
@@ -230,49 +242,6 @@ do { \
#include "stenciltmp.h"
-/*
- * This function is called to specify which buffer to read and write
- * for software rasterization (swrast) fallbacks. This doesn't necessarily
- * correspond to glDrawBuffer() or glReadBuffer() calls.
- */
-static void radeonSetBuffer( GLcontext *ctx,
- GLframebuffer *colorBuffer,
- GLuint bufferBit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- switch ( bufferBit ) {
- case BUFFER_BIT_FRONT_LEFT:
- if ( rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->backPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- } else {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->frontPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- }
- break;
- case BUFFER_BIT_BACK_LEFT:
- if ( rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->frontPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- } else {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->backPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- }
- break;
- default:
- assert(0);
- break;
- }
-}
/* Move locking out to get reasonable span performance (10x better
* than doing this in HW_LOCK above). WaitForIdle() is the main
@@ -298,8 +267,6 @@ static void radeonSpanRenderFinish( GLcontext *ctx )
void radeonInitSpanFuncs( GLcontext *ctx )
{
struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
-
- swdd->SetBuffer = radeonSetBuffer;
swdd->SpanRenderStart = radeonSpanRenderStart;
swdd->SpanRenderFinish = radeonSpanRenderFinish;
}