diff options
author | Ian Romanick <ian.d.romanick@intel.com> | 2009-09-10 15:33:45 -0700 |
---|---|---|
committer | Ian Romanick <ian.d.romanick@intel.com> | 2009-09-10 15:33:45 -0700 |
commit | b8e1e8d2d8ae6ffbf8f271b46ee89788a926b3b0 (patch) | |
tree | 5db502ab80287bfc8ff61082784017c7448464f5 /src/mesa/drivers/dri/radeon/radeon_state_init.c | |
parent | 81722c5d7e8e93d837510b9e6e5d014ec64cf4b3 (diff) | |
parent | d9dc4cb0e4f578da9e50c9d1ba6fd9c22ea2fca6 (diff) |
Merge branch 'master' into asm-shader-rework-2
Conflicts:
src/mesa/shader/lex.yy.c
src/mesa/shader/program_parse.tab.c
src/mesa/shader/program_parse.tab.h
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_state_init.c')
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state_init.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index d014fb5c06..f3ad0dd17a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -573,7 +573,7 @@ static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) for (j = 0; j < 5; j++) { OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, - RADEON_GEM_DOMAIN_VRAM, 0, 0); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } END_BATCH(); } @@ -781,6 +781,10 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); } + if (rmesa->radeon.radeonScreen->kernel_mm) { + ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); + } + for (i = 0; i < 3; i++) { if (rmesa->radeon.radeonScreen->kernel_mm) rmesa->hw.tex[i].emit = tex_emit_cs; @@ -873,6 +877,10 @@ void radeonInitState( r100ContextPtr rmesa ) } if (rmesa->radeon.radeonScreen->kernel_mm) { + rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); + rmesa->hw.stp.cmd[STP_DATA_0] = 0; + rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); + rmesa->hw.grd.emit = scl_emit; rmesa->hw.fog.emit = vec_emit; rmesa->hw.glt.emit = vec_emit; @@ -1143,7 +1151,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Y] = 0; rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; - + if (rmesa->radeon.radeonScreen->kernel_mm) { radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); |