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authorJon Smirl <jonsmirl@gmail.com>2003-10-21 06:05:39 +0000
committerJon Smirl <jonsmirl@gmail.com>2003-10-21 06:05:39 +0000
commitbcc6eddd335e97d49ed2ef3a1440f94d58dce12d (patch)
treeff4883dd4da6ce65500940aebe2c268716311fe6 /src/mesa/drivers/dri/radeon/server
parent906449753f126f74ad3321d0af897f6609880c17 (diff)
Update DRI drivers to current DRI CVS and make them work.
Diffstat (limited to 'src/mesa/drivers/dri/radeon/server')
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon.h20
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_common.h25
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_dri.c98
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_dri.h8
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_reg.h110
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_sarea.h181
6 files changed, 231 insertions, 211 deletions
diff --git a/src/mesa/drivers/dri/radeon/server/radeon.h b/src/mesa/drivers/dri/radeon/server/radeon.h
index 4606a0b71e..808289b140 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon.h
@@ -108,11 +108,11 @@ typedef struct {
* \name AGP
*/
/*@{*/
- drmSize agpSize; /**< \brief AGP map size */
- drmHandle agpMemHandle; /**< \brief AGP map handle */
- unsigned long agpOffset; /**< \brief AGP offset */
- int agpMode; /**< \brief AGP mode */
- int agpFastWrite;
+ drmSize gartSize; /**< \brief AGP map size */
+ drmHandle gartMemHandle; /**< \brief AGP map handle */
+ unsigned long gartOffset; /**< \brief AGP offset */
+ int gartMode; /**< \brief AGP mode */
+ int gartFastWrite;
/*@}*/
/**
@@ -144,11 +144,11 @@ typedef struct {
* \name CP AGP Texture data
*/
/*@{*/
- unsigned long agpTexStart; /**< \brief Offset into AGP space */
- drmHandle agpTexHandle; /**< \brief Handle from drmAddMap() */
- drmSize agpTexMapSize; /**< \brief Size of map */
- int agpTexSize; /**< \brief Size of AGP tex space (in MB) */
- int log2AGPTexGran;
+ unsigned long gartTexStart; /**< \brief Offset into AGP space */
+ drmHandle gartTexHandle; /**< \brief Handle from drmAddMap() */
+ drmSize gartTexMapSize; /**< \brief Size of map */
+ int gartTexSize; /**< \brief Size of AGP tex space (in MB) */
+ int log2GARTTexGran;
/*@}*/
int drmMinor; /**< \brief DRM device minor number */
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_common.h b/src/mesa/drivers/dri/radeon/server/radeon_common.h
index 0792b5c2e0..365ecfb9a1 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_common.h
@@ -31,7 +31,7 @@
* Converted to common header format:
* Jens Owen <jens@tungstengraphics.com>
*
- * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drmRadeon.h,v 1.6 2001/04/16 15:02:13 tsi Exp $
+ * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2003/04/07 01:22:09 martin Exp $
*
*/
@@ -70,6 +70,7 @@
#define DRM_RADEON_INIT_HEAP 0x15
#define DRM_RADEON_IRQ_EMIT 0x16
#define DRM_RADEON_IRQ_WAIT 0x17
+#define DRM_RADEON_CP_RESUME 0x18
#define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39
@@ -94,7 +95,7 @@ typedef struct {
unsigned long sarea_priv_offset;
int is_pci;
int cp_mode;
- int agp_size;
+ int gart_size;
int ring_size;
int usec_timeout;
@@ -109,7 +110,7 @@ typedef struct {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
- unsigned long agp_textures_offset;
+ unsigned long gart_textures_offset;
} drmRadeonInit;
typedef struct {
@@ -404,22 +405,22 @@ typedef struct drm_radeon_getparam {
void *value;
} drmRadeonGetParam;
-#define RADEON_PARAM_AGP_BUFFER_OFFSET 1
-#define RADEON_PARAM_LAST_FRAME 2
-#define RADEON_PARAM_LAST_DISPATCH 3
-#define RADEON_PARAM_LAST_CLEAR 4
-#define RADEON_PARAM_IRQ_NR 5
-#define RADEON_PARAM_AGP_BASE 6
+#define RADEON_PARAM_GART_BUFFER_OFFSET 1
+#define RADEON_PARAM_LAST_FRAME 2
+#define RADEON_PARAM_LAST_DISPATCH 3
+#define RADEON_PARAM_LAST_CLEAR 4
+#define RADEON_PARAM_IRQ_NR 5
+#define RADEON_PARAM_GART_BASE 6
-#define RADEON_MEM_REGION_AGP 1
-#define RADEON_MEM_REGION_FB 2
+#define RADEON_MEM_REGION_GART 1
+#define RADEON_MEM_REGION_FB 2
typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
- int *region_offset; /* offset from start of fb or agp */
+ int *region_offset; /* offset from start of fb or GART */
} drmRadeonMemAlloc;
typedef struct drm_radeon_mem_free {
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
index 4271aa7da2..a37561457b 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.c
+++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
@@ -318,7 +318,7 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
int s, l;
if (drmAgpAcquire(ctx->drmFD) < 0) {
- fprintf(stderr, "[agp] AGP not available\n");
+ fprintf(stderr, "[gart] AGP not available\n");
return 0;
}
@@ -334,40 +334,40 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
/* Disable fast write entirely - too many lockups.
*/
mode &= ~RADEON_AGP_MODE_MASK;
- switch (info->agpMode) {
+ switch (info->gartMode) {
case 4: mode |= RADEON_AGP_4X_MODE;
case 2: mode |= RADEON_AGP_2X_MODE;
case 1: default: mode |= RADEON_AGP_1X_MODE;
}
if (drmAgpEnable(ctx->drmFD, mode) < 0) {
- fprintf(stderr, "[agp] AGP not enabled\n");
+ fprintf(stderr, "[gart] AGP not enabled\n");
drmAgpRelease(ctx->drmFD);
return 0;
}
- info->agpOffset = 0;
+ info->gartOffset = 0;
- if ((ret = drmAgpAlloc(ctx->drmFD, info->agpSize*1024*1024, 0, NULL,
- &info->agpMemHandle)) < 0) {
- fprintf(stderr, "[agp] Out of memory (%d)\n", ret);
+ if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL,
+ &info->gartMemHandle)) < 0) {
+ fprintf(stderr, "[gart] Out of memory (%d)\n", ret);
drmAgpRelease(ctx->drmFD);
return 0;
}
fprintf(stderr,
- "[agp] %d kB allocated with handle 0x%08x\n",
- info->agpSize*1024, (unsigned)info->agpMemHandle);
+ "[gart] %d kB allocated with handle 0x%08x\n",
+ info->gartSize*1024, (unsigned)info->gartMemHandle);
if (drmAgpBind(ctx->drmFD,
- info->agpMemHandle, info->agpOffset) < 0) {
- fprintf(stderr, "[agp] Could not bind\n");
- drmAgpFree(ctx->drmFD, info->agpMemHandle);
+ info->gartMemHandle, info->gartOffset) < 0) {
+ fprintf(stderr, "[gart] Could not bind\n");
+ drmAgpFree(ctx->drmFD, info->gartMemHandle);
drmAgpRelease(ctx->drmFD);
return 0;
}
/* Initialize the CP ring buffer data */
- info->ringStart = info->agpOffset;
+ info->ringStart = info->gartOffset;
info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE;
info->ringReadOffset = info->ringStart + info->ringMapSize;
@@ -378,51 +378,51 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
info->bufMapSize = info->bufSize*1024*1024;
/* Reserve the rest for AGP textures */
- info->agpTexStart = info->bufStart + info->bufMapSize;
- s = (info->agpSize*1024*1024 - info->agpTexStart);
+ info->gartTexStart = info->bufStart + info->bufMapSize;
+ s = (info->gartSize*1024*1024 - info->gartTexStart);
l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->agpTexMapSize = (s >> l) << l;
- info->log2AGPTexGran = l;
+ info->gartTexMapSize = (s >> l) << l;
+ info->log2GARTTexGran = l;
if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
- fprintf(stderr, "[agp] Could not add ring mapping\n");
+ fprintf(stderr, "[gart] Could not add ring mapping\n");
return 0;
}
- fprintf(stderr, "[agp] ring handle = 0x%08lx\n", info->ringHandle);
+ fprintf(stderr, "[gart] ring handle = 0x%08lx\n", info->ringHandle);
if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
fprintf(stderr,
- "[agp] Could not add ring read ptr mapping\n");
+ "[gart] Could not add ring read ptr mapping\n");
return 0;
}
fprintf(stderr,
- "[agp] ring read ptr handle = 0x%08lx\n",
+ "[gart] ring read ptr handle = 0x%08lx\n",
info->ringReadPtrHandle);
if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
DRM_AGP, 0, &info->bufHandle) < 0) {
fprintf(stderr,
- "[agp] Could not add vertex/indirect buffers mapping\n");
+ "[gart] Could not add vertex/indirect buffers mapping\n");
return 0;
}
fprintf(stderr,
- "[agp] vertex/indirect buffers handle = 0x%08lx\n",
+ "[gart] vertex/indirect buffers handle = 0x%08lx\n",
info->bufHandle);
- if (drmAddMap(ctx->drmFD, info->agpTexStart, info->agpTexMapSize,
- DRM_AGP, 0, &info->agpTexHandle) < 0) {
+ if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
+ DRM_AGP, 0, &info->gartTexHandle) < 0) {
fprintf(stderr,
- "[agp] Could not add AGP texture map mapping\n");
+ "[gart] Could not add AGP texture map mapping\n");
return 0;
}
fprintf(stderr,
- "[agp] AGP texture map handle = 0x%08lx\n",
- info->agpTexHandle);
+ "[gart] AGP texture map handle = 0x%08lx\n",
+ info->gartTexHandle);
/* Initialize Radeon's AGP registers */
/* Ring buffer is at AGP offset 0 */
@@ -463,7 +463,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
drmInfo.is_pci = 0;
drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
- drmInfo.agp_size = info->agpSize*1024*1024;
+ drmInfo.gart_size = info->gartSize*1024*1024;
drmInfo.ring_size = info->ringSize*1024*1024;
drmInfo.usec_timeout = 1000;
drmInfo.fb_bpp = ctx->bpp;
@@ -479,7 +479,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
drmInfo.ring_offset = info->ringHandle;
drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
drmInfo.buffers_offset = info->bufHandle;
- drmInfo.agp_textures_offset = info->agpTexHandle;
+ drmInfo.gart_textures_offset = info->gartTexHandle;
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo,
sizeof(drmRadeonInit));
@@ -502,19 +502,19 @@ static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
{
drmRadeonMemInitHeap drmHeap;
- /* Start up the simple memory manager for agp space */
- drmHeap.region = RADEON_MEM_REGION_AGP;
+ /* Start up the simple memory manager for gart space */
+ drmHeap.region = RADEON_MEM_REGION_GART;
drmHeap.start = 0;
- drmHeap.size = info->agpTexMapSize;
+ drmHeap.size = info->gartTexMapSize;
if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP,
&drmHeap, sizeof(drmHeap))) {
fprintf(stderr,
- "[drm] Failed to initialized agp heap manager\n");
+ "[drm] Failed to initialized gart heap manager\n");
} else {
fprintf(stderr,
- "[drm] Initialized kernel agp heap manager, %d\n",
- info->agpTexMapSize);
+ "[drm] Initialized kernel gart heap manager, %d\n",
+ info->gartTexMapSize);
}
}
@@ -640,13 +640,13 @@ static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
info->frontPitch = ctx->shared.virtualWidth;
fprintf(stderr,
- "Using %d MB AGP aperture\n", info->agpSize);
+ "Using %d MB AGP aperture\n", info->gartSize);
fprintf(stderr,
"Using %d MB for the ring buffer\n", info->ringSize);
fprintf(stderr,
"Using %d MB for vertex/indirect buffers\n", info->bufSize);
fprintf(stderr,
- "Using %d MB for AGP textures\n", info->agpTexSize);
+ "Using %d MB for AGP textures\n", info->gartTexSize);
/* Front, back and depth buffers - everything else texture??
*/
@@ -733,7 +733,7 @@ static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
* Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its
* initialization.
*/
-static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
+static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
{
RADEONDRIPtr pRADEONDRI;
int err;
@@ -883,7 +883,7 @@ static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
/* Initialize IRQ */
RADEONDRIIrqInit(ctx, info);
- /* Initialize kernel agp memory manager */
+ /* Initialize kernel gart memory manager */
RADEONDRIAgpHeapInit(ctx, info);
/* Initialize the SAREA private data structure */
@@ -919,7 +919,7 @@ static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
pRADEONDRI->depth = ctx->bpp; /* XXX: depth */
pRADEONDRI->bpp = ctx->bpp;
pRADEONDRI->IsPCI = 0;
- pRADEONDRI->AGPMode = info->agpMode;
+ pRADEONDRI->AGPMode = info->gartMode;
pRADEONDRI->frontOffset = info->frontOffset;
pRADEONDRI->frontPitch = info->frontPitch;
pRADEONDRI->backOffset = info->backOffset;
@@ -933,10 +933,10 @@ static int RADEONScreenInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
pRADEONDRI->registerSize = info->registerSize;
pRADEONDRI->statusHandle = info->ringReadPtrHandle;
pRADEONDRI->statusSize = info->ringReadMapSize;
- pRADEONDRI->agpTexHandle = info->agpTexHandle;
- pRADEONDRI->agpTexMapSize = info->agpTexMapSize;
- pRADEONDRI->log2AGPTexGran = info->log2AGPTexGran;
- pRADEONDRI->agpTexOffset = info->agpTexStart;
+ pRADEONDRI->gartTexHandle = info->gartTexHandle;
+ pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
+ pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
+ pRADEONDRI->gartTexOffset = info->gartTexStart;
pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
/* Don't release the lock now - let the VT switch handler do it. */
@@ -1139,10 +1139,10 @@ static int radeonInitFBDev( DRIDriverContext *ctx )
ctx->driverPrivate = (void *)info;
- info->agpFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE;
- info->agpMode = RADEON_DEFAULT_AGP_MODE;
- info->agpSize = RADEON_DEFAULT_AGP_SIZE;
- info->agpTexSize = RADEON_DEFAULT_AGP_TEX_SIZE;
+ info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE;
+ info->gartMode = RADEON_DEFAULT_AGP_MODE;
+ info->gartSize = RADEON_DEFAULT_AGP_SIZE;
+ info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE;
info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
info->ringSize = RADEON_DEFAULT_RING_SIZE;
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.h b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
index fce21227cb..fc96deb102 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
@@ -102,10 +102,10 @@ typedef struct {
* \name CP AGP Texture data
*/
/*@{*/
- drmHandle agpTexHandle; /**< \brief AGP texture area map handle */
- drmSize agpTexMapSize; /**< \brief AGP texture area map size */
- int log2AGPTexGran; /**< \brief AGP texture granularity in log base 2 */
- int agpTexOffset; /**< \brief AGP texture area offset in AGP space */
+ drmHandle gartTexHandle; /**< \brief AGP texture area map handle */
+ drmSize gartTexMapSize; /**< \brief AGP texture area map size */
+ int log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */
+ int gartTexOffset; /**< \brief AGP texture area offset in AGP space */
/*@}*/
unsigned int sarea_priv_offset; /**< \brief offset of the private SAREA data*/
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
index 5570a43945..4bd4d14e78 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.25 2003/02/07 18:08:59 martin Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.30 2003/10/07 22:47:12 martin Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -66,6 +66,8 @@
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
+#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
+# define RADEON_AGP_ENABLE (1<<8)
#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
#define RADEON_AGP_STATUS 0x0f5c /* PCI */
# define RADEON_AGP_1X_MODE 0x01
@@ -232,6 +234,28 @@
# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
#define RADEON_CRC_CMDFIFO_ADDR 0x0740
#define RADEON_CRC_CMDFIFO_DOUT 0x0744
+#define RADEON_GRPH_BUFFER_CNTL 0x02f0
+# define RADEON_GRPH_START_REQ_MASK (0x7f)
+# define RADEON_GRPH_START_REQ_SHIFT 0
+# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
+# define RADEON_GRPH_STOP_REQ_SHIFT 8
+# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
+# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
+# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
+# define RADEON_GRPH_BUFFER_SIZE (1<<29)
+# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
+# define RADEON_GRPH_STOP_CNTL (1<<31)
+#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
+# define RADEON_GRPH2_START_REQ_MASK (0x7f)
+# define RADEON_GRPH2_START_REQ_SHIFT 0
+# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
+# define RADEON_GRPH2_STOP_REQ_SHIFT 8
+# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
+# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
+# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
+# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
+# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
+# define RADEON_GRPH2_STOP_CNTL (1<<31)
#define RADEON_CRTC_CRNT_FRAME 0x0214
#define RADEON_CRTC_EXT_CNTL 0x0054
# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
@@ -272,6 +296,9 @@
# define RADEON_CRTC2_CSYNC_EN (1 << 27)
# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
+#define RADEON_CRTC_MORE_CNTL 0x27c
+# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
+# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
@@ -356,7 +383,10 @@
#define RADEON_DAC_CNTL 0x0058
# define RADEON_DAC_RANGE_CNTL (3 << 0)
+# define RADEON_DAC_RANGE_CNTL_MASK 0x03
# define RADEON_DAC_BLANKING (1 << 2)
+# define RADEON_DAC_CMP_EN (1 << 3)
+# define RADEON_DAC_CMP_OUTPUT (1 << 7)
# define RADEON_DAC_8BIT_EN (1 << 8)
# define RADEON_DAC_VGA_ADR_EN (1 << 13)
# define RADEON_DAC_PDWN (1 << 15)
@@ -365,6 +395,12 @@
# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
+#define RADEON_DAC_EXT_CNTL 0x0280
+# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
+# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
+# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
+# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
+# define RADEON_DAC_FORCE_DATA_SHIFT 8
#define RADEON_TV_DAC_CNTL 0x088c
# define RADEON_TV_DAC_STD_MASK 0x0300
# define RADEON_TV_DAC_RDACPD (1 << 24)
@@ -374,7 +410,9 @@
# define RADEON_CRT2_DISP1_SEL (1 << 5)
#define RADEON_DISP_OUTPUT_CNTL 0x0d64
# define RADEON_DISP_DAC_SOURCE_MASK 0x03
+# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
+# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
#define RADEON_DAC_CRC_SIG 0x02cc
#define RADEON_DAC_DATA 0x03c9 /* VGA */
#define RADEON_DAC_MASK 0x03c6 /* VGA */
@@ -392,6 +430,23 @@
#define RADEON_DEVICE_ID 0x0f02 /* PCI */
#define RADEON_DISP_MISC_CNTL 0x0d00
# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
+#define RADEON_DISP_MERGE_CNTL 0x0d60
+# define RADEON_DISP_ALPHA_MODE_MASK 0x03
+# define RADEON_DISP_ALPHA_MODE_KEY 0
+# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
+# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
+# define RADEON_DISP_RGB_OFFSET_EN (1<<8)
+# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
+# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
+# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
+#define RADEON_DISP2_MERGE_CNTL 0x0d68
+# define RADEON_DISP2_RGB_OFFSET_EN (1<<8)
+#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
+#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
+#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
+#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
+#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
+#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
#define RADEON_DP_CNTL 0x16c0
@@ -582,7 +637,10 @@
# define RADEON_FP2_BLANK_EN (1 << 1)
# define RADEON_FP2_ON (1 << 2)
# define RADEON_FP2_PANEL_FORMAT (1 << 3)
-# define RADEON_FP2_SEL_CRTC2 (1 << 13)
+# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10)
+# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10)
+# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
+# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
# define RADEON_FP2_FP_POL (1 << 16)
# define RADEON_FP2_LP_POL (1 << 17)
# define RADEON_FP2_SCK_POL (1 << 18)
@@ -590,6 +648,8 @@
# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
# define RADEON_FP2_CRC_EN (1 << 23)
# define RADEON_FP2_CRC_READ_EN (1 << 24)
+# define RADEON_FP2_DV0_EN (1 << 25)
+# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26)
#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
#define RADEON_FP_HORZ_STRETCH 0x028c
@@ -697,6 +757,10 @@
#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
#define RADEON_MC_AGP_LOCATION 0x014c
#define RADEON_MC_FB_LOCATION 0x0148
+#define RADEON_DISPLAY_BASE_ADDR 0x23c
+#define RADEON_DISPLAY2_BASE_ADDR 0x33c
+#define RADEON_OV0_BASE_ADDR 0x43c
+#define RADEON_NB_TOM 0x15c
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
@@ -711,6 +775,12 @@
#define RADEON_MEM_ADDR_CONFIG 0x0148
#define RADEON_MEM_BASE 0x0f10 /* PCI */
#define RADEON_MEM_CNTL 0x0140
+# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
+# define RADEON_MEM_USE_B_CH_ONLY (1<<1)
+# define RV100_HALF_MODE (1<<3)
+# define R300_MEM_NUM_CHANNELS_MASK 0x03
+# define R300_MEM_USE_CD_CH_ONLY (1<<2)
+#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
#define RADEON_MEM_INIT_LAT_TIMER 0x0154
#define RADEON_MEM_INTF_CNTL 0x014c
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
@@ -723,7 +793,13 @@
#define RADEON_MPLL_CNTL 0x000e /* PLL */
#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
-
+#define R300_MC_IND_INDEX 0x01f8
+# define R300_MC_IND_ADDR_MASK 0x3f
+#define R300_MC_IND_DATA 0x01fc
+#define R300_MC_READ_CNTL_AB 0x017c
+# define R300_MEM_RBS_POSITION_A_MASK 0x03
+#define R300_MC_READ_CNTL_CD_mcind 0x24
+# define R300_MEM_RBS_POSITION_C_MASK 0x03
#define RADEON_N_VIF_COUNT 0x0248
@@ -879,7 +955,7 @@
# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff < 18)
+# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
# define R300_PPLL_REF_DIV_ACC_SHIFT 18
#define RADEON_PALETTE_DATA 0x00b4
#define RADEON_PALETTE_30_DATA 0x00b8
@@ -891,6 +967,11 @@
# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
+# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
+# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
+# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
+# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
+# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
#define RADEON_PLANE_3D_MASK_C 0x1d44
#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
@@ -1013,6 +1094,9 @@
#define RADEON_TEST_DEBUG_MUX 0x0124
#define RADEON_TEST_DEBUG_OUT 0x012c
#define RADEON_TMDS_PLL_CNTL 0x02a8
+#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
+# define RADEON_TMDS_TRANSMITTER_PLLEN 1
+# define RADEON_TMDS_TRANSMITTER_PLLRST 2
#define RADEON_TRAIL_BRES_DEC 0x1614
#define RADEON_TRAIL_BRES_ERR 0x160c
#define RADEON_TRAIL_BRES_INC 0x1610
@@ -1025,6 +1109,9 @@
# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
+# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
+# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
+
#define RADEON_VENDOR_ID 0x0f00 /* PCI */
#define RADEON_VGA_DDA_CONFIG 0x02e8
#define RADEON_VGA_DDA_ON_OFF 0x02ec
@@ -1878,12 +1965,11 @@
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
+#define RADEON_AIC_LO_ADDR 0x01dc
/* Constants */
-#define RADEON_AGP_TEX_OFFSET 0x02000000
-
#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
@@ -2012,4 +2098,16 @@
#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
#define RADEON_SS_SHININESS 60
+#define RADEON_TV_MASTER_CNTL 0x0800
+# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
+#define RADEON_TV_DAC_CNTL 0x088c
+# define RADEON_TV_DAC_CMPOUT (1 << 5)
+#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
+# define RADEON_Y_RED_EN (1 << 0)
+# define RADEON_C_GRN_EN (1 << 1)
+# define RADEON_CMP_BLU_EN (1 << 2)
+# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
+# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
+# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
+# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
#endif
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_sarea.h b/src/mesa/drivers/dri/radeon/server/radeon_sarea.h
index 81e4325d7a..95db1f37ac 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_sarea.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_sarea.h
@@ -1,11 +1,4 @@
-/**
- * \file server/radeon_sarea.h
- * \brief SAREA definition.
- *
- * \author Kevin E. Martin <martin@xfree86.org>
- * \author Gareth Hughes <gareth@valinux.com>
- */
-
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.5 2002/10/30 12:52:14 alanh Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
@@ -34,7 +27,12 @@
* DEALINGS IN THE SOFTWARE.
*/
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.4 2002/04/24 16:20:41 martin Exp $ */
+/*
+ * Authors:
+ * Kevin E. Martin <martin@xfree86.org>
+ * Gareth Hughes <gareth@valinux.com>
+ *
+ */
#ifndef _RADEON_SAREA_H_
#define _RADEON_SAREA_H_
@@ -94,11 +92,11 @@
/* Keep these small for testing */
#define RADEON_NR_SAREA_CLIPRECTS 12
-/* There are 2 heaps (local/AGP). Each region within a heap is a
+/* There are 2 heaps (local/GART). Each region within a heap is a
* minimum of 64k, and there are at most 64 of them per heap.
*/
#define RADEON_CARD_HEAP 0
-#define RADEON_AGP_HEAP 1
+#define RADEON_GART_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16
@@ -115,10 +113,6 @@
#endif /* __RADEON_SAREA_DEFINES__ */
-
-/**
- * \brief Color register format.
- */
typedef struct {
unsigned int red;
unsigned int green;
@@ -126,15 +120,8 @@ typedef struct {
unsigned int alpha;
} radeon_color_regs_t;
-
-/**
- * \brief Context registers.
- */
typedef struct {
- /**
- * \name Context state
- */
- /*@{*/
+ /* Context state */
unsigned int pp_misc;
unsigned int pp_fog_color;
unsigned int re_solid_color;
@@ -149,76 +136,44 @@ typedef struct {
unsigned int re_width_height;
unsigned int rb3d_colorpitch;
unsigned int se_cntl;
- /*@}*/
- /**
- * \name Vertex format state
- */
- /*@{*/
+ /* Vertex format state */
unsigned int se_coord_fmt;
- /*@}*/
- /**
- * \name Line state
- */
- /*@{*/
+ /* Line state */
unsigned int re_line_pattern;
unsigned int re_line_state;
unsigned int se_line_width;
- /*@}*/
- /**
- * \name Bumpmap state
- */
- /*@{*/
+ /* Bumpmap state */
unsigned int pp_lum_matrix;
unsigned int pp_rot_matrix_0;
unsigned int pp_rot_matrix_1;
- /*@}*/
- /**
- * \name Mask state
- */
- /*@{*/
+ /* Mask state */
unsigned int rb3d_stencilrefmask;
unsigned int rb3d_ropcntl;
unsigned int rb3d_planemask;
- /*@}*/
- /**
- * \name Viewport state
- */
- /*@{*/
+ /* Viewport state */
unsigned int se_vport_xscale;
unsigned int se_vport_xoffset;
unsigned int se_vport_yscale;
unsigned int se_vport_yoffset;
unsigned int se_vport_zscale;
unsigned int se_vport_zoffset;
- /*@}*/
- /**
- * \name Setup state
- */
- /*@{*/
+ /* Setup state */
unsigned int se_cntl_status;
- /*@}*/
- /**
- * \name Misc state
- */
- /*@{*/
+ /* Misc state */
unsigned int re_top_left;
unsigned int re_misc;
- /*@}*/
} radeon_context_regs_t;
-
-/**
- * \brief Setup registers for each texture unit
- */
+/* Setup registers for each texture unit */
typedef struct {
unsigned int pp_txfilter;
unsigned int pp_txformat;
@@ -229,82 +184,48 @@ typedef struct {
unsigned int pp_border_color;
} radeon_texture_regs_t;
-/**
- * \brief Maintain an LRU of contiguous regions of texture space.
- *
- * If you think you own a region of texture memory, and it has an age different
- * to the one you set, then you are mistaken and it has been stolen by another
- * client. If global RADEONSAREAPriv::texAge hasn't changed, there is no need to walk the list.
- *
- * These regions can be used as a proxy for the fine-grained texture
- * information of other clients - by maintaining them in the same LRU which is
- * used to age their own textures, clients have an approximate LRU for the
- * whole of global texture space, and can make informed decisions as to which
- * areas to kick out. There is no need to choose whether to kick out your own
- * texture or someone else's - simply eject them all in LRU order.
- *
- * \sa RADEONSAREAPriv::texList.
- */
-typedef struct {
- unsigned char next; /**< \brief indices to form a circular LRU */
- unsigned char prev; /**< \brief indices to form a circular LRU */
- unsigned char in_use; /**< \brief owned by a client, or free? */
- int age; /**< \brief tracked by clients to update local LRU's */
-} radeon_tex_region_t;
-
-
-/**
- * \brief Private SAREA definition
- *
- * The channel for communication of state information to the kernel
- * on firing a vertex buffer.
- */
typedef struct {
- radeon_context_regs_t ContextState; /** \brief Context registers */
+ /* The channel for communication of state information to the kernel
+ * on firing a vertex buffer.
+ */
+ radeon_context_regs_t ContextState;
radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
- /**< \brief Texture registers */
- unsigned int dirty;
- unsigned int vertsize; /**< \brief vertex size */
- unsigned int vc_format; /**< \brief vertex format */
+ unsigned int dirty;
+ unsigned int vertsize;
+ unsigned int vc_format;
- /**
- * \name Cliprects
- *
- * The current cliprects, or a subset thereof.
- */
- /*@{*/
- XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
- /**< \brief cliprects */
- unsigned int nbox; /**< \brief number of cliprects */
- /*@}*/
-
- /**
- * \name Counters
- *
- * Counters for throttling rendering of clients.
- */
- /*@{*/
- unsigned int last_frame; /**< \brief last emmited frame */
+ /* The current cliprects, or a subset thereof */
+ XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
+ unsigned int nbox;
+
+ /* Counters for throttling of rendering clients */
+ unsigned int last_frame;
unsigned int last_dispatch;
- unsigned int last_clear; /**< \brief last emmited clear */
- /*@}*/
+ unsigned int last_clear;
- /**
- * \name LRU
- */
- /*@{*/
- /** \brief Texture regions.
- * Last element is sentinal
+ /* Maintain an LRU of contiguous regions of texture space. If you
+ * think you own a region of texture memory, and it has an age
+ * different to the one you set, then you are mistaken and it has
+ * been stolen by another client. If global texAge hasn't changed,
+ * there is no need to walk the list.
+ *
+ * These regions can be used as a proxy for the fine-grained texture
+ * information of other clients - by maintaining them in the same
+ * lru which is used to age their own textures, clients have an
+ * approximate lru for the whole of global texture space, and can
+ * make informed decisions as to which areas to kick out. There is
+ * no need to choose whether to kick out your own texture or someone
+ * else's - simply eject them all in LRU order.
*/
+ /* Last elt is sentinal */
drmTextureRegion texList[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
- /** \brief last time texture was uploaded */
+ /* last time texture was uploaded */
unsigned int texAge[RADEON_NR_TEX_HEAPS];
- /*@}*/
- int ctxOwner; /**< \brief last context to upload state */
- int pfAllowPageFlip; /**< \brief set by the 2d driver, read by the client */
- int pfCurrentPage; /**< \brief set by kernel, read by others */
- int crtc2_base; /**< \brief for pageflipping with CloneMode */
+ int ctxOwner; /* last context to upload state */
+ int pfAllowPageFlip; /* set by the 2d driver, read by the client */
+ int pfCurrentPage; /* set by kernel, read by others */
+ int crtc2_base; /* for pageflipping with CloneMode */
} RADEONSAREAPriv, *RADEONSAREAPrivPtr;
#endif