Merge branch 'master' into asm-shader-rework-1

Conflicts:
	src/mesa/shader/arbprogparse.c

22 files changed, 676 insertions, 315 deletions

diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
index 8eeaea1cb2..8789e3ab09 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
@@ -34,10 +34,6 @@
 #include <stdint.h>
 //#include "radeon_track.h"
 
-#ifndef RADEON_DEBUG_BO
-#define RADEON_DEBUG_BO 0
-#endif
-
 /* bo object */
 #define RADEON_BO_FLAGS_MACRO_TILE  1
 #define RADEON_BO_FLAGS_MICRO_TILE  2
@@ -61,28 +57,22 @@ struct radeon_bo {
 
 /* bo functions */
 struct radeon_bo_funcs {
-#ifdef RADEON_DEBUG_BO
-    struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom,
-                                 uint32_t handle,
-                                 uint32_t size,
-                                 uint32_t alignment,
-                                 uint32_t domains,
-                                 uint32_t flags,
-                                 char * szBufUsage);
-#else
     struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom,
                                  uint32_t handle,
                                  uint32_t size,
                                  uint32_t alignment,
                                  uint32_t domains,
                                  uint32_t flags);
-#endif /* RADEON_DEBUG_BO */
     void (*bo_ref)(struct radeon_bo *bo);
     struct radeon_bo *(*bo_unref)(struct radeon_bo *bo);
     int (*bo_map)(struct radeon_bo *bo, int write);
     int (*bo_unmap)(struct radeon_bo *bo);
     int (*bo_wait)(struct radeon_bo *bo);
     int (*bo_is_static)(struct radeon_bo *bo);
+    int (*bo_set_tiling)(struct radeon_bo *bo, uint32_t tiling_flags,
+			  uint32_t pitch);
+    int (*bo_get_tiling)(struct radeon_bo *bo, uint32_t *tiling_flags,
+			  uint32_t *pitch);
 };
 
 struct radeon_bo_manager {
@@ -110,20 +100,13 @@ static inline struct radeon_bo *_radeon_bo_open(struct radeon_bo_manager *bom,
                                                 uint32_t alignment,
                                                 uint32_t domains,
                                                 uint32_t flags,
-#ifdef RADEON_DEBUG_BO
-                                                char * szBufUsage,
-#endif /* RADEON_DEBUG_BO */
                                                 const char *file,
                                                 const char *func,
                                                 int line)
 {
     struct radeon_bo *bo;
 
-#ifdef RADEON_DEBUG_BO
-    bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags, szBufUsage);
-#else
     bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags);
-#endif /* RADEON_DEBUG_BO */
 
 #ifdef RADEON_BO_TRACK
     if (bo) {
@@ -187,6 +170,18 @@ static inline int _radeon_bo_wait(struct radeon_bo *bo,
     return bo->bom->funcs->bo_wait(bo);
 }
 
+static inline int radeon_bo_set_tiling(struct radeon_bo *bo,
+				       uint32_t tiling_flags, uint32_t pitch)
+{
+    return bo->bom->funcs->bo_set_tiling(bo, tiling_flags, pitch);
+}
+
+static inline int radeon_bo_get_tiling(struct radeon_bo *bo,
+				       uint32_t *tiling_flags, uint32_t *pitch)
+{
+    return bo->bom->funcs->bo_get_tiling(bo, tiling_flags, pitch);
+}
+
 static inline int radeon_bo_is_static(struct radeon_bo *bo)
 {
 	if (bo->bom->funcs->bo_is_static)
@@ -194,13 +189,8 @@ static inline int radeon_bo_is_static(struct radeon_bo *bo)
 	return 0;
 }
 
-#ifdef RADEON_DEBUG_BO
-#define radeon_bo_open(bom, h, s, a, d, f, u)\
-    _radeon_bo_open(bom, h, s, a, d, f, u, __FILE__, __FUNCTION__, __LINE__)
-#else
 #define radeon_bo_open(bom, h, s, a, d, f)\
     _radeon_bo_open(bom, h, s, a, d, f, __FILE__, __FUNCTION__, __LINE__)
-#endif /* RADEON_DEBUG_BO */
 #define radeon_bo_ref(bo)\
     _radeon_bo_ref(bo, __FILE__, __FUNCTION__, __LINE__)
 #define radeon_bo_unref(bo)\
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index 992eb4611b..5575da6971 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -69,9 +69,6 @@ struct bo_legacy {
     void                *ptr;
     struct bo_legacy    *next, *prev;
     struct bo_legacy    *pnext, *pprev;
-#ifdef RADEON_DEBUG_BO
-    char                szBufUsage[16];
-#endif /* RADEON_DEBUG_BO */
 };
 
 struct bo_manager_legacy {
@@ -289,12 +286,7 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
                                      uint32_t size,
                                      uint32_t alignment,
                                      uint32_t domains,
-#ifdef RADEON_DEBUG_BO
-                                     uint32_t flags,
-                                     char * szBufUsage)
-#else
                                      uint32_t flags)
-#endif /* RADEON_DEBUG_BO */
 {
     struct bo_legacy *bo_legacy;
     static int pgsize;
@@ -327,10 +319,6 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
         bo_legacy->next->prev = bo_legacy;
     }
 
-#ifdef RADEON_DEBUG_BO
-    sprintf(bo_legacy->szBufUsage, "%s", szBufUsage); 
-#endif /* RADEON_DEBUG_BO */
-
     return bo_legacy;
 }
 
@@ -429,12 +417,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
                                  uint32_t size,
                                  uint32_t alignment,
                                  uint32_t domains,
-#ifdef RADEON_DEBUG_BO
-                                 uint32_t flags,
-                                 char *   szBufUsage)
-#else
                                  uint32_t flags)
-#endif /* RADEON_DEBUG_BO */
 {
     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
     struct bo_legacy *bo_legacy;
@@ -451,11 +434,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
         }
         return NULL;
     }
-#ifdef RADEON_DEBUG_BO
-    bo_legacy = bo_allocate(boml, size, alignment, domains, flags, szBufUsage);
-#else
     bo_legacy = bo_allocate(boml, size, alignment, domains, flags);
-#endif /* RADEON_DEBUG_BO */
     bo_legacy->static_bo = 0;
     r = legacy_new_handle(boml, &bo_legacy->base.handle);
     if (r) {
@@ -577,6 +556,8 @@ static struct radeon_bo_funcs bo_legacy_funcs = {
     bo_unmap,
     NULL,
     bo_is_static,
+    NULL,
+    NULL,
 };
 
 static int bo_vram_validate(struct radeon_bo *bo,
@@ -622,12 +603,34 @@ static int bo_vram_validate(struct radeon_bo *bo,
 
     if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) {
 	    if (IS_R600_CLASS(boml->screen)) {
-		    char *src = bo_legacy->ptr;
-		    char *dst = (char *) boml->screen->driScreen->pFB +
-			    (bo_legacy->offset - boml->fb_location);
+		    drm_radeon_texture_t tex;
+		    drm_radeon_tex_image_t tmp;
+		    int ret;
 
-		    /* FIXME: alignment, pitch, etc. */
-		    memcpy(dst, src, bo->size);
+		    tex.offset = bo_legacy->offset;
+		    tex.image = &tmp;
+		    assert(!(tex.offset & 1023));
+
+		    tmp.x = 0;
+		    tmp.y = 0;
+		    tmp.width = bo->size;
+		    tmp.height = 1;
+		    tmp.data = bo_legacy->ptr;
+		    tex.format = RADEON_TXFORMAT_ARGB8888;
+		    tex.width = tmp.width;
+		    tex.height = tmp.height;
+		    tex.pitch = bo->size;
+		    do {
+			    ret = drmCommandWriteRead(bo->bom->fd,
+						      DRM_RADEON_TEXTURE,
+						      &tex,
+						      sizeof(drm_radeon_texture_t));
+			    if (ret) {
+				    if (RADEON_DEBUG & DEBUG_IOCTL)
+					    fprintf(stderr, "DRM_RADEON_TEXTURE:  again!\n");
+				    usleep(1);
+			    }
+		    } while (ret == -EAGAIN);
 	    } else {
 		    /* Copy to VRAM using a blit.
 		     * All memory is 4K aligned. We're using 1024 pixels wide blits.
@@ -689,14 +692,8 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo,
     int retries = 0;
 
     if (bo_legacy->map_count) {
-#ifdef RADEON_DEBUG_BO
-        fprintf(stderr, "bo(%p, %d, %s) is mapped (%d) can't valide it.\n",
-                bo, bo->size, bo_legacy->szBufUsage, bo_legacy->map_count);
-#else
         fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n",
                 bo, bo->size, bo_legacy->map_count);
-#endif /* RADEON_DEBUG_BO */
-
         return -EINVAL;
     }
     if (bo_legacy->static_bo || bo_legacy->validated) {
@@ -768,21 +765,13 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom)
 }
 
 static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy *bom,
-						       int size, 
-#ifdef RADEON_DEBUG_BO
-                               uint32_t offset,
-                               char * szBufUsage)
-#else
-                               uint32_t offset)
-#endif /* RADEON_DEBUG_BO */
+						       int size,
+						       uint32_t offset)
 {
     struct bo_legacy *bo;
 
-#ifdef RADEON_DEBUG_BO
-    bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0, szBufUsage);
-#else
     bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-#endif /* RADEON_DEBUG_BO */
+
     if (bo == NULL)
 	return NULL;
     bo->static_bo = 1;
@@ -843,11 +832,8 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
     size = 4096*4096*4; 
 
     /* allocate front */
-#ifdef RADEON_DEBUG_BO
-    bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset, "FRONT BUF");
-#else
     bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset);
-#endif /* RADEON_DEBUG_BO */
+
     if (!bo) {
         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
         return NULL;
@@ -857,11 +843,8 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
     }
 
     /* allocate back */
-#ifdef RADEON_DEBUG_BO
-    bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset, "BACK BUF");
-#else
     bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset);
-#endif /* RADEON_DEBUG_BO */
+
     if (!bo) {
         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
         return NULL;
@@ -871,11 +854,8 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
     }
 
     /* allocate depth */
-#ifdef RADEON_DEBUG_BO
-    bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset, "Z BUF");
-#else
     bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset);
-#endif /* RADEON_DEBUG_BO */
+
     if (!bo) {
         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
         return NULL;
@@ -904,3 +884,29 @@ unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo)
     return bo->size;
 }
 
+/*
+ * Fake up a bo for things like texture image_override.
+ * bo->offset already includes fb_location
+ */
+struct radeon_bo *radeon_legacy_bo_alloc_fake(struct radeon_bo_manager *bom,
+					      int size,
+	                                      uint32_t offset)
+{
+    struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
+    struct bo_legacy *bo;
+
+    bo = bo_allocate(boml, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+
+    if (bo == NULL)
+	return NULL;
+    bo->static_bo = 1;
+    bo->offset = offset;
+    bo->base.handle = bo->offset;
+    bo->ptr = boml->screen->driScreen->pFB + (offset - boml->fb_location);
+    if (bo->base.handle > boml->nhandle) {
+        boml->nhandle = bo->base.handle + 1;
+    }
+    radeon_bo_ref(&(bo->base));
+    return &(bo->base);
+}
+
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
index 0db817cab0..455adebc09 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
@@ -42,5 +42,8 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
 void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom);
 void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom);
 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo);
+struct radeon_bo *radeon_legacy_bo_alloc_fake(struct radeon_bo_manager *bom,
+					      int size,
+	                                      uint32_t offset);
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
index e0c70dd9a1..a42870f4a9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
@@ -15,6 +15,12 @@
 #define RADEON_GEM_DOMAIN_GTT 0x2   // GTT or cache flushed
 #define RADEON_GEM_DOMAIN_VRAM 0x4  // VRAM domain
 
+#define RADEON_TILING_MACRO 0x1
+#define RADEON_TILING_MICRO 0x2
+#define RADEON_TILING_SWAP 0x4
+#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
+				   * when mapped - i.e. front buffer */
+
 /* to be used to build locally in mesa with no libdrm bits */
 #include "../radeon/radeon_bo_drm.h"
 #include "../radeon/radeon_cs_drm.h"
diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c
new file mode 100644
index 0000000000..e8ae51e6ea
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2009 Maciej Cencora <m.cencora@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "radeon_buffer_objects.h"
+
+#include "main/imports.h"
+#include "main/mtypes.h"
+#include "main/bufferobj.h"
+
+#include "radeon_common.h"
+
+struct radeon_buffer_object *
+get_radeon_buffer_object(struct gl_buffer_object *obj)
+{
+    return (struct radeon_buffer_object *) obj;
+}
+
+static struct gl_buffer_object *
+radeonNewBufferObject(GLcontext * ctx,
+                      GLuint name,
+                      GLenum target)
+{
+    struct radeon_buffer_object *obj = CALLOC_STRUCT(radeon_buffer_object);
+
+    _mesa_initialize_buffer_object(&obj->Base, name, target);
+
+    obj->bo = NULL;
+
+    return &obj->Base;
+}
+
+/**
+ * Called via glDeleteBuffersARB().
+ */
+static void
+radeonDeleteBufferObject(GLcontext * ctx,
+                         struct gl_buffer_object *obj)
+{
+    struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
+
+    if (obj->Pointer) {
+        radeon_bo_unmap(radeon_obj->bo);
+    }
+
+    if (radeon_obj->bo) {
+        radeon_bo_unref(radeon_obj->bo);
+    }
+
+    _mesa_free(radeon_obj);
+}
+
+
+/**
+ * Allocate space for and store data in a buffer object.  Any data that was
+ * previously stored in the buffer object is lost.  If data is NULL,
+ * memory will be allocated, but no copy will occur.
+ * Called via glBufferDataARB().
+ */
+static void
+radeonBufferData(GLcontext * ctx,
+                 GLenum target,
+                 GLsizeiptrARB size,
+                 const GLvoid * data,
+                 GLenum usage,
+                 struct gl_buffer_object *obj)
+{
+    radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+    struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
+
+    radeon_obj->Base.Size = size;
+    radeon_obj->Base.Usage = usage;
+
+    if (radeon_obj->bo != NULL) {
+        radeon_bo_unref(radeon_obj->bo);
+        radeon_obj->bo = NULL;
+    }
+
+    if (size != 0) {
+        radeon_obj->bo = radeon_bo_open(radeon->radeonScreen->bom,
+                                        0,
+                                        size,
+                                        32,
+                                        RADEON_GEM_DOMAIN_GTT,
+                                        0);
+
+        if (data != NULL) {
+            radeon_bo_map(radeon_obj->bo, GL_TRUE);
+
+            _mesa_memcpy(radeon_obj->bo->ptr, data, size);
+
+            radeon_bo_unmap(radeon_obj->bo);
+        }
+    }
+}
+
+/**
+ * Replace data in a subrange of buffer object.  If the data range
+ * specified by size + offset extends beyond the end of the buffer or
+ * if data is NULL, no copy is performed.
+ * Called via glBufferSubDataARB().
+ */
+static void
+radeonBufferSubData(GLcontext * ctx,
+                    GLenum target,
+                    GLintptrARB offset,
+                    GLsizeiptrARB size,
+                    const GLvoid * data,
+                    struct gl_buffer_object *obj)
+{
+    struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
+
+    radeon_bo_map(radeon_obj->bo, GL_TRUE);
+
+    _mesa_memcpy(radeon_obj->bo->ptr + offset, data, size);
+
+    radeon_bo_unmap(radeon_obj->bo);
+}
+
+/**
+ * Called via glGetBufferSubDataARB()
+ */
+static void
+radeonGetBufferSubData(GLcontext * ctx,
+                       GLenum target,
+                       GLintptrARB offset,
+                       GLsizeiptrARB size,
+                       GLvoid * data,
+                       struct gl_buffer_object *obj)
+{
+    struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
+
+    radeon_bo_map(radeon_obj->bo, GL_FALSE);
+
+    _mesa_memcpy(data, radeon_obj->bo->ptr + offset, size);
+
+    radeon_bo_unmap(radeon_obj->bo);
+}
+
+/**
+ * Called via glMapBufferARB()
+ */
+static void *
+radeonMapBuffer(GLcontext * ctx,
+                GLenum target,
+                GLenum access,
+                struct gl_buffer_object *obj)
+{
+    struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
+
+    if (access == GL_WRITE_ONLY_ARB) {
+        ctx->Driver.Flush(ctx);
+    }
+
+    if (radeon_obj->bo == NULL) {
+        obj->Pointer = NULL;
+        return NULL;
+    }
+
+    radeon_bo_map(radeon_obj->bo, access == GL_WRITE_ONLY_ARB);
+
+    return obj->Pointer = radeon_obj->bo->ptr;
+}
+
+
+/**
+ * Called via glUnmapBufferARB()
+ */
+static GLboolean
+radeonUnmapBuffer(GLcontext * ctx,
+                  GLenum target,
+                  struct gl_buffer_object *obj)
+{
+    struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj);
+
+    if (radeon_obj->bo != NULL) {
+        radeon_bo_unmap(radeon_obj->bo);
+        obj->Pointer = NULL;
+    }
+
+    return GL_TRUE;
+}
+
+void
+radeonInitBufferObjectFuncs(struct dd_function_table *functions)
+{
+    functions->NewBufferObject = radeonNewBufferObject;
+    functions->DeleteBuffer = radeonDeleteBufferObject;
+    functions->BufferData = radeonBufferData;
+    functions->BufferSubData = radeonBufferSubData;
+    functions->GetBufferSubData = radeonGetBufferSubData;
+    functions->MapBuffer = radeonMapBuffer;
+    functions->UnmapBuffer = radeonUnmapBuffer;
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer_objects.h b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.h
new file mode 100644
index 0000000000..d681960825
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2009 Maciej Cencora <m.cencora@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RADEON_BUFFER_OBJECTS_H
+#define RADEON_BUFFER_OBJECTS_H
+
+#include "main/mtypes.h"
+
+struct radeon_bo;
+
+/**
+ * Radeon vertex/pixel buffer object, derived from Mesa's gl_buffer_object.
+ */
+struct radeon_buffer_object
+{
+   struct gl_buffer_object Base;
+   struct radeon_bo *bo;
+};
+
+struct radeon_buffer_object *
+get_radeon_buffer_object(struct gl_buffer_object *obj);
+
+/**
+ * Hook the bufferobject implementation into mesa:
+ */
+void radeonInitBufferObjectFuncs(struct dd_function_table *functions);
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index 0a6a2df35b..a275c8fb14 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -356,11 +356,14 @@
 #define PCI_CHIP_RV770_947A             0x947A
 #define PCI_CHIP_RV770_947B             0x947B
 
+#define PCI_CHIP_RV730_9480             0x9480
 #define PCI_CHIP_RV730_9487             0x9487
+#define PCI_CHIP_RV730_9488             0x9488
 #define PCI_CHIP_RV730_9489             0x9489
 #define PCI_CHIP_RV730_948F             0x948F
 #define PCI_CHIP_RV730_9490             0x9490
 #define PCI_CHIP_RV730_9491             0x9491
+#define PCI_CHIP_RV730_9495             0x9495
 #define PCI_CHIP_RV730_9498             0x9498
 #define PCI_CHIP_RV730_949C             0x949C
 #define PCI_CHIP_RV730_949E             0x949E
@@ -374,12 +377,16 @@
 #define PCI_CHIP_RV710_9552             0x9552
 #define PCI_CHIP_RV710_9553             0x9553
 #define PCI_CHIP_RV710_9555             0x9555
+#define PCI_CHIP_RV710_9557             0x9557
 
 #define PCI_CHIP_RV740_94A0             0x94A0
 #define PCI_CHIP_RV740_94A1             0x94A1
+#define PCI_CHIP_RV740_94A3             0x94A3
 #define PCI_CHIP_RV740_94B1             0x94B1
 #define PCI_CHIP_RV740_94B3             0x94B3
+#define PCI_CHIP_RV740_94B4             0x94B4
 #define PCI_CHIP_RV740_94B5             0x94B5
+#define PCI_CHIP_RV740_94B9             0x94B9
 
 enum {
    CHIP_FAMILY_R100,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index dde615a4d9..0614c89459 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -481,32 +481,6 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 		if (!n)
 			continue;
 
-		if (IS_R600_CLASS(rmesa->radeonScreen)) {
-			int cpp = rmesa->radeonScreen->cpp;
-			int src_pitch = rmesa->radeonScreen->backPitch * cpp;
-			int dst_pitch = rmesa->radeonScreen->frontPitch * cpp;
-			char *src = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->backOffset;
-			char *dst = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->frontOffset;
-			int j;
-			drm_clip_rect_t *pb = rmesa->sarea->boxes;
-
-			for (j = 0; j < n; j++) {
-				int x = pb[j].x1;
-				int y = pb[j].y1;
-				int w = pb[j].x2 - x;
-				int h = pb[j].y2 - y;
-
-				src += (y * src_pitch) + (x * cpp);
-				dst += (y * dst_pitch) + (x * cpp);
-
-				while (h--) {
-					memcpy(dst, src, w * cpp);
-					src += src_pitch;
-					dst += dst_pitch;
-				}
-			}
-		}
-
 		ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
 
 		if ( ret ) {
@@ -887,10 +861,11 @@ void radeonUpdatePageFlipping(radeonContextPtr radeon)
 
 void radeon_window_moved(radeonContextPtr radeon)
 {
+	/* Cliprects has to be updated before doing anything else */
+	radeonSetCliprects(radeon);
 	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
 		radeonUpdatePageFlipping(radeon);
 	}
-	radeonSetCliprects(radeon);
 }
 
 void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height)
@@ -905,7 +880,7 @@ void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei he
 
 	if (!radeon->meta.internal_viewport_call && ctx->DrawBuffer->Name == 0) {
 		if (radeon->is_front_buffer_rendering) {
-			radeonFlush(ctx);
+			ctx->Driver.Flush(ctx);
 		}
 		radeon_update_renderbuffers(driContext, driContext->driDrawablePriv);
 		if (driContext->driDrawablePriv != driContext->driReadablePriv)
@@ -1092,7 +1067,7 @@ void radeonFlush(GLcontext *ctx)
 			 * each of N places that do rendering.  This has worse performances,
 			 * but it is much easier to get correct.
 			 */
-			if (radeon->is_front_buffer_rendering) {
+			if (!radeon->is_front_buffer_rendering) {
 				radeon->front_buffer_dirty = GL_FALSE;
 			}
 		}
@@ -1236,7 +1211,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
 	rmesa->cmdbuf.size = size;
 
 	radeon_cs_space_set_flush(rmesa->cmdbuf.cs,
-				  (void (*)(void *))radeonFlush, rmesa->glCtx);
+				  (void (*)(void *))rmesa->glCtx->Driver.Flush, rmesa->glCtx);
 
 	if (!rmesa->radeonScreen->kernel_mm) {
 		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 285e015c92..c0abcbfa21 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -85,6 +85,17 @@ static const char* get_chip_family_name(int chip_family)
 	case CHIP_FAMILY_R580: return "R580";
 	case CHIP_FAMILY_RV560: return "RV560";
 	case CHIP_FAMILY_RV570: return "RV570";
+	case CHIP_FAMILY_R600: return "R600";
+	case CHIP_FAMILY_RV610: return "RV610";
+	case CHIP_FAMILY_RV630: return "RV630";
+	case CHIP_FAMILY_RV670: return "RV670";
+	case CHIP_FAMILY_RV620: return "RV620";
+	case CHIP_FAMILY_RV635: return "RV635";
+	case CHIP_FAMILY_RS780: return "RS780";
+	case CHIP_FAMILY_RV770: return "RV770";
+	case CHIP_FAMILY_RV730: return "RV730";
+	case CHIP_FAMILY_RV710: return "RV710";
+	case CHIP_FAMILY_RV740: return "RV740";
 	default: return "unknown";
 	}
 }
@@ -200,6 +211,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 	radeon->dri.screen = sPriv;
 	radeon->dri.hwContext = driContextPriv->hHWContext;
 	radeon->dri.hwLock = &sPriv->pSAREA->lock;
+	radeon->dri.hwLockCount = 0;
 	radeon->dri.fd = sPriv->fd;
 	radeon->dri.drmMinor = sPriv->drm_version.minor;
 
@@ -230,7 +242,26 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
                 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
 	        DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
-	radeon->texture_row_align = 32;
+	if (IS_R600_CLASS(radeon->radeonScreen)) {
+		radeon->texture_row_align = 256;
+		radeon->texture_rect_row_align = 256;
+		radeon->texture_compressed_row_align = 256;
+	} else if (IS_R200_CLASS(radeon->radeonScreen) ||
+		   IS_R100_CLASS(radeon->radeonScreen)) {
+		radeon->texture_row_align = 32;
+		radeon->texture_rect_row_align = 64;
+		radeon->texture_compressed_row_align = 32;
+	} else { /* R300 - not sure this is all correct */
+		int chip_family = radeon->radeonScreen->chip_family;
+		if (chip_family == CHIP_FAMILY_RS600 ||
+		    chip_family == CHIP_FAMILY_RS690 ||
+		    chip_family == CHIP_FAMILY_RS740)
+			radeon->texture_row_align = 64;
+		else
+			radeon->texture_row_align = 32;
+		radeon->texture_rect_row_align = 64;
+		radeon->texture_compressed_row_align = 64;
+	}
 
 	return GL_TRUE;
 }
@@ -264,11 +295,10 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 	GET_CURRENT_CONTEXT(ctx);
 	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
 	radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
-
-    /* +r6/r7 */
-    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
-    /* --------- */
+#endif
 
 	if (radeon == current) {
 		radeon_firevertices(radeon);
@@ -276,16 +306,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 	}
 
 	assert(radeon);
-	if (radeon) 
-    {
-
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
-	    if (IS_R600_CLASS(screen))
-        {
-		r600DestroyContext(driContextPriv);
-        }
-#endif
-
+	if (radeon) {
 		if (radeon->dma.current) {
 			rcommonFlushCmdBuf( radeon, __FUNCTION__ );
 		}
@@ -356,88 +377,48 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
 
 	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->frontOffset,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Front Buf");
-#else
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->frontOffset,
 						0,
 						0,
 						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
 	}
 	if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->backOffset,
 						0,
 						0,
 						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Back Buf");
-#else
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->backOffset,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
 	}
 	if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->depthOffset,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Z Buf");
-#else
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset,
 						0,
 						0,
 						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 	}
 	if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->depthOffset,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Stencil Buf");
-#else
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset,
 						0,
 						0,
 						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
@@ -460,16 +441,6 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 
 	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->frontOffset +
-						radeon->radeonScreen->fbLocation,
-						size,
-						4096,
-						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Front Buf");
-#else
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->frontOffset +
 						radeon->radeonScreen->fbLocation,
@@ -477,23 +448,12 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 						4096,
 						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
 	}
 	if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->backOffset +
-						radeon->radeonScreen->fbLocation,
-						size,
-						4096,
-						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Back Buf");
-#else
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->backOffset +
 						radeon->radeonScreen->fbLocation,
@@ -501,55 +461,32 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 						4096,
 						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
 	}
 	if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset +
 						radeon->radeonScreen->fbLocation,
 						size,
 						4096,
 						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Z Buf");
-#else
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->depthOffset +
-						radeon->radeonScreen->fbLocation,
-						size,
-						4096,
-						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 	}
 	if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
 		if (!rb->bo) {
-#ifdef RADEON_DEBUG_BO
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset +
 						radeon->radeonScreen->fbLocation,
 						size,
 						4096,
 						RADEON_GEM_DOMAIN_VRAM,
-						0,
-                        "Stencil Buf");
-#else
-            rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						radeon->radeonScreen->depthOffset +
-						radeon->radeonScreen->fbLocation,
-						size,
-						4096,
-						RADEON_GEM_DOMAIN_VRAM,
 						0);
-#endif /* RADEON_DEBUG_BO */
 		}
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
@@ -732,28 +669,29 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			bo = depth_bo;
 			radeon_bo_ref(bo);
 		} else {
-#ifdef RADEON_DEBUG_BO
-            bo = radeon_bo_open(radeon->radeonScreen->bom,
-						buffers[i].name,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						buffers[i].flags,
-                        regname);
-#else
+			uint32_t tiling_flags = 0, pitch = 0;
+			int ret;
+
 			bo = radeon_bo_open(radeon->radeonScreen->bom,
 						buffers[i].name,
 						0,
 						0,
 						RADEON_GEM_DOMAIN_VRAM,
 						buffers[i].flags);
-#endif /* RADEON_DEBUG_BO */
+
 			if (bo == NULL) {
 
 				fprintf(stderr, "failed to attach %s %d\n",
 					regname, buffers[i].name);
 
 			}
+
+			ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
+			if (tiling_flags & RADEON_TILING_MACRO)
+				bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
+			if (tiling_flags & RADEON_TILING_MICRO)
+				bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
+			
 		}
 
 		if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index e4a8da0596..ee46c1f81a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -239,6 +239,11 @@ struct radeon_tex_obj {
 	GLuint SQ_TEX_SAMPLER1;
 	GLuint SQ_TEX_SAMPLER2;
 
+	GLuint TD_PS_SAMPLER0_BORDER_RED;
+	GLuint TD_PS_SAMPLER0_BORDER_GREEN;
+	GLuint TD_PS_SAMPLER0_BORDER_BLUE;
+	GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
+
 	GLboolean border_fallback;
 
 
@@ -360,6 +365,7 @@ struct radeon_dri_mirror {
 
 	drm_context_t hwContext;
 	drm_hw_lock_t *hwLock;
+	int hwLockCount;
 	int fd;
 	int drmMinor;
 };
@@ -424,6 +430,8 @@ struct radeon_context {
    int                   texture_depth;
    float                 initialMaxAnisotropy;
    uint32_t              texture_row_align;
+   uint32_t              texture_rect_row_align;
+   uint32_t              texture_compressed_row_align;
 
   struct radeon_dma dma;
   struct radeon_hw_state hw;
@@ -438,7 +446,6 @@ struct radeon_context {
    GLuint numClipRects;	/* Cliprects for the draw buffer */
    drm_clip_rect_t *pClipRects;
    unsigned int lastStamp;
-   GLboolean lost_context;
    drm_radeon_sarea_t *sarea;	/* Private SAREA data */
 
    /* Mirrors of some DRI state */
@@ -587,10 +594,4 @@ extern int RADEON_DEBUG;
 #define RADEON_DEBUG		0
 #endif
 
-#ifndef HAVE_LIBDRM_RADEON
-#ifndef RADEON_DEBUG_BO
-#define RADEON_DEBUG_BO 1
-#endif
-#endif
-
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_space_drm.c b/src/mesa/drivers/dri/radeon/radeon_cs_space_drm.c
index 5a8df7bb8c..89cbbb5a6b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_space_drm.c
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_space_drm.c
@@ -82,7 +82,7 @@ static inline int radeon_cs_setup_bo(struct radeon_cs_space_check *sc, struct ra
 	    if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
 		sizes->op_read -= bo->size;
 		sizes->op_vram_write += bo->size;
-	    } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
+	    } else if (write_domain == RADEON_GEM_DOMAIN_GTT) {
 		sizes->op_read -= bo->size;
 		sizes->op_gart_write += bo->size;
 	    }
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 48114a0012..5e755c51ed 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -52,7 +52,7 @@ do {						\
 } while (0)
 #endif
 
-static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count)
+void radeonEmitVec4(uint32_t *out, const GLvoid * data, int stride, int count)
 {
 	int i;
 
@@ -70,7 +70,7 @@ static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count)
 		}
 }
 
-void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count)
+void radeonEmitVec8(uint32_t *out, const GLvoid * data, int stride, int count)
 {
 	int i;
 
@@ -89,7 +89,7 @@ void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count)
 		}
 }
 
-void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count)
+void radeonEmitVec12(uint32_t *out, const GLvoid * data, int stride, int count)
 {
 	int i;
 
@@ -110,7 +110,7 @@ void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count)
 		}
 }
 
-static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count)
+void radeonEmitVec16(uint32_t *out, const GLvoid * data, int stride, int count)
 {
 	int i;
 
@@ -132,7 +132,7 @@ static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count)
 }
 
 void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos,
-			 GLvoid * data, int size, int stride, int count)
+			 const GLvoid * data, int size, int stride, int count)
 {
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 	uint32_t *out;
@@ -185,15 +185,9 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size)
 	}
 
 again_alloc:
-#ifdef RADEON_DEBUG_BO
-    rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom,
-					    0, size, 4, RADEON_GEM_DOMAIN_GTT,
-					    0, "dma.current");
-#else    
 	rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom,
 					    0, size, 4, RADEON_GEM_DOMAIN_GTT,
 					    0);
-#endif /* RADEON_DEBUG_BO */
 
 	if (!rmesa->dma.current) {
 		rcommonFlushCmdBuf(rmesa, __FUNCTION__);
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.h b/src/mesa/drivers/dri/radeon/radeon_dma.h
index 06e388fc1d..55509ed00c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.h
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.h
@@ -33,11 +33,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef RADEON_DMA_H
 #define RADEON_DMA_H
 
-void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count);
-void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count);
+void radeonEmitVec4(uint32_t *out, const GLvoid * data, int stride, int count);
+void radeonEmitVec8(uint32_t *out, const GLvoid * data, int stride, int count);
+void radeonEmitVec12(uint32_t *out, const GLvoid * data, int stride, int count);
+void radeonEmitVec16(uint32_t *out, const GLvoid * data, int stride, int count);
 
 void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos,
-			 GLvoid * data, int size, int stride, int count);
+			 const GLvoid * data, int size, int stride, int count);
 
 void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size);
 void radeonAllocDmaRegion(radeonContextPtr rmesa,
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index f28efa33e9..8303917b0b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -185,22 +185,12 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
 
      rrb->pitch = pitch * cpp;
      rrb->cpp = cpp;
-#ifdef RADEON_DEBUG_BO
-     rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-			      0,
-			      size,
-			      0,
-			      RADEON_GEM_DOMAIN_VRAM,
-			      0,
-                  "Radeon RBO");
-#else
      rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 			      0,
 			      size,
 			      0,
 			      RADEON_GEM_DOMAIN_VRAM,
 			      0);
-#endif /* RADEON_DEBUG_BO */
      rb->Width = width;
      rb->Height = height;
        return GL_TRUE;
@@ -291,7 +281,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
 	    rrb->base.RedBits = 8;
 	    rrb->base.GreenBits = 8;
 	    rrb->base.BlueBits = 8;
-	    rrb->base.AlphaBits = 8;
+	    rrb->base.AlphaBits = 0;
 	    rrb->base.DataType = GL_UNSIGNED_BYTE;
 	    break;
 	case GL_RGBA8:
@@ -407,7 +397,7 @@ restart:
 		rrb->cpp = 2;
 		rrb->base._ActualFormat = GL_RGB5;
 		rrb->base._BaseFormat = GL_RGB;
-		rrb->base.DataType = GL_UNSIGNED_SHORT;
+		rrb->base.DataType = GL_UNSIGNED_BYTE;
 		DBG("Render to RGB5 texture OK\n");
 	}
 	else if (texImage->TexFormat == &_mesa_texformat_argb1555) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index 5774f7ebcf..6294b7e42b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -85,11 +85,35 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 	}
 
 	rmesa->vtbl.get_lock(rmesa);
-
-	rmesa->lost_context = GL_TRUE;
 }
-
-void radeon_lock_hardware(radeonContextPtr radeon)
+#ifndef NDEBUG
+struct lock_debug {
+	const char* function;
+	const char* file;
+	int line;
+};
+
+static struct lock_debug ldebug = {0};
+#endif
+
+#if 0
+/** TODO: use atomic operations for reference counting **/
+/** gcc 4.2 has builtin functios for this **/
+#define ATOMIC_INC_AND_FETCH(atomic) __sync_add_and_fetch(&atomic, 1)
+#define ATOMIC_DEC_AND_FETCH(atomic) __sync_sub_and_fetch(&atomic, 1)
+#else
+#define ATOMIC_INC_AND_FETCH(atomic) (++atomic)
+#define ATOMIC_DEC_AND_FETCH(atomic) (--atomic)
+#endif
+
+
+void radeon_lock_hardware(radeonContextPtr radeon
+#ifndef NDEBUG
+		,const char* function
+		,const char* file
+		,const int line
+#endif
+		)
 {
 	char ret = 0;
 	struct radeon_framebuffer *rfb = NULL;
@@ -104,16 +128,39 @@ void radeon_lock_hardware(radeonContextPtr radeon)
 	}
 
 	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+		if (ATOMIC_INC_AND_FETCH(radeon->dri.hwLockCount) > 1)
+		{
+#ifndef NDEBUG
+			if ( RADEON_DEBUG & DEBUG_SANITY )
+				fprintf(stderr, "*** %d times of recursive call to %s ***\n"
+						"Original call was from %s (file: %s line: %d)\n"
+						"Now call is coming from %s (file: %s line: %d)\n"
+						, radeon->dri.hwLockCount, __FUNCTION__
+						, ldebug.function, ldebug.file, ldebug.line
+						, function, file, line
+					   );
+#endif
+			return;
+		}
 		DRM_CAS(radeon->dri.hwLock, radeon->dri.hwContext,
 			 (DRM_LOCK_HELD | radeon->dri.hwContext), ret );
 		if (ret)
 			radeonGetLock(radeon, 0);
+#ifndef NDEBUG
+		ldebug.function = function;
+		ldebug.file = file;
+		ldebug.line = line;
+#endif
 	}
 }
 
 void radeon_unlock_hardware(radeonContextPtr radeon)
 {
 	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+		if (ATOMIC_DEC_AND_FETCH(radeon->dri.hwLockCount) > 0)
+		{
+			return;
+		}
 		DRM_UNLOCK( radeon->dri.fd,
 			    radeon->dri.hwLock,
 			    radeon->dri.hwContext );
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h
index 2817709eed..da5a5b4371 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.h
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.h
@@ -48,12 +48,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags);
 
-void radeon_lock_hardware(radeonContextPtr rmesa);
+void radeon_lock_hardware(radeonContextPtr rmesa
+#ifndef NDEBUG
+		,const char* function
+		,const char* file
+		,const int line
+#endif
+		);
 void radeon_unlock_hardware(radeonContextPtr rmesa);
 
 /* Lock the hardware and validate our state.
  */
+#ifdef NDEBUG
 #define LOCK_HARDWARE( rmesa )	radeon_lock_hardware(rmesa)
+#else
+#define LOCK_HARDWARE( rmesa )	radeon_lock_hardware(rmesa, __FUNCTION__, __FILE__, __LINE__)
+#endif
 #define UNLOCK_HARDWARE( rmesa )  radeon_unlock_hardware(rmesa)
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index f04a07fecd..eba9f5857f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -90,16 +90,18 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = &mt->levels[level];
-	uint32_t row_align = rmesa->texture_row_align - 1;
+	uint32_t row_align;
 
 	/* Find image size in bytes */
 	if (mt->compressed) {
 		/* TODO: Is this correct? Need test cases for compressed textures! */
-		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
+		row_align = rmesa->texture_compressed_row_align - 1;
+		lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
 		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
 							   lvl->width, lvl->height, lvl->depth, mt->compressed);
 	} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
-		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
+		row_align = rmesa->texture_rect_row_align - 1;
+		lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
 		lvl->size = lvl->rowstride * lvl->height;
 	} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
 		/* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
@@ -108,6 +110,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
 		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
 	} else {
+		row_align = rmesa->texture_row_align - 1;
 		lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
 		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
 	}
@@ -212,18 +215,10 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	else
 		calculate_miptree_layout_r100(rmesa, mt);
 
-#ifdef RADEON_DEBUG_BO
-    mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
-                            0, mt->totalsize, 1024,
-                            RADEON_GEM_DOMAIN_VRAM,
-                            0,
-                            "MIPMAP TREE");
-#else
 	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,
                             RADEON_GEM_DOMAIN_VRAM,
                             0);
-#endif /* RADEON_DEBUG_BO */
 
 	return mt;
 }
@@ -323,7 +318,8 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 	if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel)
 		return GL_FALSE;
 
-	if (texImage->IsCompressed != mt->compressed)
+	if ((!texImage->IsCompressed && mt->compressed) ||
+	    (texImage->IsCompressed && !mt->compressed))
 		return GL_FALSE;
 
 	if (!texImage->IsCompressed &&
@@ -363,8 +359,8 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu
 	        mt->width0 == firstImage->Width &&
 	        mt->height0 == firstImage->Height &&
 	        mt->depth0 == firstImage->Depth &&
-	        mt->bpp == firstImage->TexFormat->TexelBytes &&
-	        mt->compressed == compressed);
+	        mt->compressed == compressed &&
+	        (!mt->compressed ? (mt->bpp == firstImage->TexFormat->TexelBytes) : 1));
 }
 
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 290ef2394d..c8d491621a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -57,7 +57,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_tex.h"
 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 #include "r300_context.h"
-#include "r300_fragprog.h"
 #include "r300_tex.h"
 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
 #include "r600_context.h"
@@ -150,6 +149,9 @@ extern const struct dri_extension point_extensions[];
 
 #elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
 
+#define DRI_CONF_FP_OPTIMIZATION_SPEED   0
+#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
+
 /* TODO: integrate these into xmlpool.h! */
 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
@@ -876,11 +878,14 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
       screen->chip_flags = RADEON_CHIPSET_TCL;
       break;
 
+   case PCI_CHIP_RV730_9480:
    case PCI_CHIP_RV730_9487:
+   case PCI_CHIP_RV730_9488:
    case PCI_CHIP_RV730_9489:
    case PCI_CHIP_RV730_948F:
    case PCI_CHIP_RV730_9490:
    case PCI_CHIP_RV730_9491:
+   case PCI_CHIP_RV730_9495:
    case PCI_CHIP_RV730_9498:
    case PCI_CHIP_RV730_949C:
    case PCI_CHIP_RV730_949E:
@@ -897,15 +902,19 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
    case PCI_CHIP_RV710_9552:
    case PCI_CHIP_RV710_9553:
    case PCI_CHIP_RV710_9555:
+   case PCI_CHIP_RV710_9557:
       screen->chip_family = CHIP_FAMILY_RV710;
       screen->chip_flags = RADEON_CHIPSET_TCL;
       break;
 
    case PCI_CHIP_RV740_94A0:
    case PCI_CHIP_RV740_94A1:
+   case PCI_CHIP_RV740_94A3:
    case PCI_CHIP_RV740_94B1:
    case PCI_CHIP_RV740_94B3:
+   case PCI_CHIP_RV740_94B4:
    case PCI_CHIP_RV740_94B5:
+   case PCI_CHIP_RV740_94B9:
       screen->chip_family = CHIP_FAMILY_RV740;
       screen->chip_flags = RADEON_CHIPSET_TCL;
       break;
@@ -990,6 +999,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
       screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
       screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
       screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
+      screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
    }
 
    ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
@@ -1025,7 +1035,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
 		   ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
    else
 	   screen->scratch = (__volatile__ uint32_t *)
-		   ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
+		   ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
 
    screen->buffers = drmMapBufs( sPriv->fd );
    if ( !screen->buffers ) {
@@ -1085,7 +1095,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    /* +r6/r7 */
    if(screen->chip_family >= CHIP_FAMILY_R600)
    {
-       if (ret) 
+       if (ret)
        {
             FREE( screen );
             fprintf(stderr, "Unable to get fb location need newer drm\n");
@@ -1098,18 +1108,18 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    }
    else
    {
-        if (ret) 
+        if (ret)
         {
             if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
 	            screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
-            else 
+            else
             {
                 FREE( screen );
                 fprintf(stderr, "Unable to get fb location need newer drm\n");
                 return NULL;
             }
-        } 
-        else 
+        }
+        else
         {
             screen->fbLocation = (temp & 0xffff) << 16;
         }
@@ -1289,6 +1299,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
    screen->drmSupportsPointSprites = 1;
    screen->drmSupportsCubeMapsR100 = 1;
    screen->drmSupportsVertexProgram = 1;
+   screen->drmSupportsOcclusionQueries = 1;
    screen->irq = 1;
 
    ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
@@ -1577,21 +1588,11 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
 {
 	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
-	if (IS_R600_CLASS(screen))
-		return r600CreateContext(glVisual, driContextPriv, sharedContextPriv);
-#endif
-
 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 	if (IS_R300_CLASS(screen))
 		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
-	if (IS_R200_CLASS(screen))
-		return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
-#endif
-
 #if !RADEON_COMMON
 	(void)screen;
 	return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
@@ -1791,8 +1792,16 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 const struct __DriverAPIRec driDriverAPI = {
    .InitScreen      = radeonInitScreen,
    .DestroyScreen   = radeonDestroyScreen,
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+   .CreateContext   = r200CreateContext,
+   .DestroyContext  = r200DestroyContext,
+#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+   .CreateContext   = r600CreateContext,
+   .DestroyContext  = r600DestroyContext,
+#else
    .CreateContext   = radeonCreateContext,
    .DestroyContext  = radeonDestroyContext,
+#endif
    .CreateBuffer    = radeonCreateBuffer,
    .DestroyBuffer   = radeonDestroyBuffer,
    .SwapBuffers     = radeonSwapBuffers,
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 2a2f6b1b0b..f0dd46b0b1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -99,6 +99,7 @@ typedef struct radeon_screen {
    GLboolean drmSupportsPointSprites;   /* need radeon kernel module >= 1.13 */
    GLboolean drmSupportsCubeMapsR100;   /* need radeon kernel module >= 1.15 */
    GLboolean drmSupportsVertexProgram;  /* need radeon kernel module >= 1.25 */
+   GLboolean drmSupportsOcclusionQueries; /* need radeon kernel module >= 1.30 */
    GLboolean depthHasSurface;
 
    /* Configuration cache with default values for all contexts */
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index b2a468b4fd..5e4bf00d7a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -51,6 +51,59 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
 
+
+/* r200 depth buffer is always tiled - this is the formula
+   according to the docs unless I typo'ed in it
+*/
+static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb,
+				 GLint x, GLint y)
+{
+    GLubyte *ptr = rrb->bo->ptr;
+    GLint offset;
+    if (rrb->has_surface) {
+	offset = x * rrb->cpp + y * rrb->pitch;
+    } else {
+	GLuint b;
+	offset = 0;
+	b = (((y  >> 4) * (rrb->pitch >> 8) + (x >> 6)));
+	offset += (b >> 1) << 12;
+	offset += (((rrb->pitch >> 8) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
+	offset += ((y >> 2) & 0x3) << 9;
+	offset += ((x >> 3) & 0x1) << 8;
+	offset += ((x >> 4) & 0x3) << 6;
+	offset += ((x >> 2) & 0x1) << 5;
+	offset += ((y >> 1) & 0x1) << 4;
+	offset += ((x >> 1) & 0x1) << 3;
+	offset += (y & 0x1) << 2;
+	offset += (x & 0x1) << 1;
+    }
+    return &ptr[offset];
+}
+
+static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb,
+				 GLint x, GLint y)
+{
+    GLubyte *ptr = rrb->bo->ptr;
+    GLint offset;
+    if (rrb->has_surface) {
+	offset = x * rrb->cpp + y * rrb->pitch;
+    } else {
+	GLuint b;
+	offset = 0;
+	b = (((y & 0x7ff) >> 4) * (rrb->pitch >> 7) + (x >> 5));
+	offset += (b >> 1) << 12;
+	offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
+	offset += ((y >> 2) & 0x3) << 9;
+	offset += ((x >> 2) & 0x1) << 8;
+	offset += ((x >> 3) & 0x3) << 6;
+	offset += ((y >> 1) & 0x1) << 5;
+	offset += ((x >> 1) & 0x1) << 4;
+	offset += (y & 0x1) << 3;
+	offset += (x & 0x1) << 2;
+    }
+    return &ptr[offset];
+}
+
 /* radeon tiling on r300-r500 has 4 states,
    macro-linear/micro-linear
    macro-linear/micro-tiled
@@ -61,7 +114,6 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
    4 byte surface
    8/16 byte (unused)
 */
-   
 static GLubyte *radeon_ptr_4byte(const struct radeon_renderbuffer * rrb,
 			     GLint x, GLint y)
 {
@@ -285,11 +337,21 @@ s8z24_to_z24s8(uint32_t val)
  */
 #define VALUE_TYPE GLushort
 
+#if defined(RADEON_COMMON_FOR_R200)
+#define WRITE_DEPTH( _x, _y, d )					\
+   *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d
+#else
 #define WRITE_DEPTH( _x, _y, d )					\
    *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d
+#endif
 
+#if defined(RADEON_COMMON_FOR_R200)
+#define READ_DEPTH( d, _x, _y )						\
+   d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off)
+#else
 #define READ_DEPTH( d, _x, _y )						\
    d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off)
+#endif
 
 #define TAG(x) radeon##x##_z16
 #include "depthtmp.h"
@@ -301,7 +363,7 @@ s8z24_to_z24s8(uint32_t val)
  */
 #define VALUE_TYPE GLuint
 
-#ifdef COMPILE_R300
+#if defined(COMPILE_R300)
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
@@ -310,6 +372,15 @@ do {									\
    tmp |= ((d << 8) & 0xffffff00);					\
    *_ptr = tmp;					\
 } while (0)
+#elif defined(RADEON_COMMON_FOR_R200)
+#define WRITE_DEPTH( _x, _y, d )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off );		\
+   GLuint tmp = *_ptr;				\
+   tmp &= 0xff000000;							\
+   tmp |= ((d) & 0x00ffffff);						\
+   *_ptr = tmp;					\
+} while (0)
 #else
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
@@ -321,19 +392,21 @@ do {									\
 } while (0)
 #endif
 
-#ifdef COMPILE_R300
+#if defined(COMPILE_R300)
 #define READ_DEPTH( d, _x, _y )						\
   do {									\
     d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \
   }while(0)
+#elif defined(RADEON_COMMON_FOR_R200)
+#define READ_DEPTH( d, _x, _y )						\
+  do {									\
+    d = *(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off)) & 0x00ffffff; \
+  }while(0)
 #else
 #define READ_DEPTH( d, _x, _y )	\
   d = *(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off,	_y + y_off)) & 0x00ffffff;
 #endif
-/*
-    fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\
-   d = *(GLuint*)(radeon_ptr(rrb, _x,	_y )) & 0x00ffffff;
-*/
+
 #define TAG(x) radeon##x##_z24
 #include "depthtmp.h"
 
@@ -345,12 +418,19 @@ do {									\
  */
 #define VALUE_TYPE GLuint
 
-#ifdef COMPILE_R300
+#if defined(COMPILE_R300)
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
    *_ptr = d;								\
 } while (0)
+#elif defined(RADEON_COMMON_FOR_R200)
+#define WRITE_DEPTH( _x, _y, d )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off );		\
+   GLuint tmp = z24s8_to_s8z24(d);					\
+   *_ptr = tmp;								\
+} while (0)
 #else
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
@@ -360,20 +440,22 @@ do {									\
 } while (0)
 #endif
 
-#ifdef COMPILE_R300
+#if defined(COMPILE_R300)
 #define READ_DEPTH( d, _x, _y )						\
   do { \
     d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)));	\
   }while(0)
+#elif defined(RADEON_COMMON_FOR_R200)
+#define READ_DEPTH( d, _x, _y )						\
+  do { \
+    d = s8z24_to_z24s8(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off)));	\
+  }while(0)
 #else
 #define READ_DEPTH( d, _x, _y )	do {					\
     d = s8z24_to_z24s8(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off,	_y + y_off ))); \
   } while (0)
 #endif
-/*
-    fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\
-   d = *(GLuint*)(radeon_ptr(rrb, _x,	_y )) & 0x00ffffff;
-*/
+
 #define TAG(x) radeon##x##_z24_s8
 #include "depthtmp.h"
 
@@ -392,6 +474,15 @@ do {									\
    tmp |= (d) & 0xff;							\
    *_ptr = tmp;					\
 } while (0)
+#elif defined(RADEON_COMMON_FOR_R200)
+#define WRITE_STENCIL( _x, _y, d )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x + x_off, _y + y_off);		\
+   GLuint tmp = *_ptr;				\
+   tmp &= 0x00ffffff;							\
+   tmp |= (((d) & 0xff) << 24);						\
+   *_ptr = tmp;					\
+} while (0)
 #else
 #define WRITE_STENCIL( _x, _y, d )					\
 do {									\
@@ -410,6 +501,13 @@ do {									\
    GLuint tmp = *_ptr;				\
    d = tmp & 0x000000ff;						\
 } while (0)
+#elif defined(RADEON_COMMON_FOR_R200)
+#define READ_STENCIL( d, _x, _y )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off );		\
+   GLuint tmp = *_ptr;				\
+   d = (tmp & 0xff000000) >> 24;					\
+} while (0)
 #else
 #define READ_STENCIL( d, _x, _y )					\
 do {									\
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index aaa82b1d6a..57aa7f1ca4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -423,7 +423,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    if (drb)
      dwords += 6;
    if (rrb)
-     dwords += 6;
+     dwords += 8;
    BEGIN_BATCH_NO_AUTOSTATE(dwords);
 
    /* In the CS case we need to split this up */
@@ -449,7 +449,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
      OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
-     OUT_BATCH(cbpitch);
+     OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
    }
 
    // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index ad501c454c..fa16f44c18 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -610,9 +610,17 @@ static void radeon_teximage(
 
 	if (pixels) {
 		radeon_teximage_map(image, GL_TRUE);
-
 		if (compressed) {
-			memcpy(texImage->Data, pixels, imageSize);
+			if (image->mt) {
+				uint32_t srcRowStride, bytesPerRow, rows;
+				srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width);
+				bytesPerRow = srcRowStride;
+				rows = (height + 3) / 4;
+				copy_rows(texImage->Data, image->mt->levels[level].rowstride,
+					  pixels, srcRowStride, rows, bytesPerRow);
+			} else {
+				memcpy(texImage->Data, pixels, imageSize);
+			}
 		} else {
 			GLuint dstRowStride;
 			GLuint *dstImageOffsets;
@@ -756,14 +764,23 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int leve
 		}
 
 		if (compressed) {
-			uint32_t srcRowStride, bytesPerRow, rows; 
-			dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width);
+			uint32_t srcRowStride, bytesPerRow, rows;
+			GLubyte *img_start;
+			if (!image->mt) {
+				dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width);
+				img_start = _mesa_compressed_image_address(xoffset, yoffset, 0,
+									   texImage->TexFormat->MesaFormat,
+									   texImage->Width, texImage->Data);
+			}
+			else {
+				uint32_t blocks_x = dstRowStride / (image->mt->bpp * 4);
+				img_start = texImage->Data + image->mt->bpp * 4 * (blocks_x * (yoffset / 4) + xoffset / 4);
+			}
 			srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width);
 			bytesPerRow = srcRowStride;
-			rows = height / 4;
+			rows = (height + 3) / 4;
 
-			copy_rows(texImage->Data, dstRowStride,  image->base.Data, srcRowStride, rows,
-				  bytesPerRow);
+			copy_rows(img_start, dstRowStride,  pixels, srcRowStride, rows,  bytesPerRow);
 			
 		} else {
 			if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat,
@@ -884,8 +901,8 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag
 		uint32_t height;
 		/* need to confirm this value is correct */
 		if (mt->compressed) {
-			height = image->base.Height / 4;
-			srcrowstride = image->base.RowStride * mt->bpp;
+			height = (image->base.Height + 3) / 4;
+			srcrowstride = _mesa_compressed_row_stride(image->base.TexFormat->MesaFormat, image->base.Width);
 		} else {
 			height = image->base.Height * image->base.Depth;
 			srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes;
@@ -951,7 +968,7 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t
 			fprintf(stderr, " Allocate new miptree\n");
 		radeon_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel);
 		if (!t->mt) {
-			_mesa_problem(ctx, "r300_validate_texture failed to alloc miptree");
+			_mesa_problem(ctx, "radeon_validate_texture failed to alloc miptree");
 			return GL_FALSE;
 		}
 	}
@@ -1000,6 +1017,8 @@ radeon_get_tex_image(GLcontext * ctx, GLenum target, GLint level,
 	}
 
 	if (compressed) {
+		/* FIXME: this can't work for small textures (mips) which
+		         use different hw stride */
 		_mesa_get_compressed_teximage(ctx, target, level, pixels,
 					      texObj, texImage);
 	} else {