summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/radeon
diff options
context:
space:
mode:
authorMichel Dänzer <daenzer@vmware.com>2010-03-12 19:00:47 +0100
committerMichel Dänzer <daenzer@vmware.com>2010-03-12 19:00:47 +0100
commitb13e305ee1a2454265fd957a99640a2e49507bea (patch)
treee62dfd0ff761ec89de478499130d58d4b119aa0d /src/mesa/drivers/dri/radeon
parentd1ca1599f0319f5c99852ce24420aa592e806db0 (diff)
parent8561bec0ac1ae5a8871c86f1f2cc29d44cb0f878 (diff)
Merge branch '7.8'
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state.c2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 78c5f5dd57..7f5fb99fa4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -553,6 +553,8 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
}
if (mtCount == 0) {
+ free(mtSizes);
+ free(mts);
return NULL;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index ebae0792aa..0afbc19c12 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -1901,7 +1901,7 @@ void radeonUploadTexMatrix( r100ContextPtr rmesa,
So: if we need the q coord in the end (solely determined by the texture
target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
Additionally, if we don't have texgen but 4 tex coords submitted, we swap
- column 3 and 4 (for the 2d / 1d / texrect targets) since the the q coord
+ column 3 and 4 (for the 2d / 1d / texrect targets) since the q coord
will get submitted in the "wrong", i.e. 3rd, slot.
If an app submits 3 coords for 2d targets, we assume it is saving on vertex
size and using the texture matrix to swap the r and q coords around (ut2k3