R6xx/R7xx: WIP r6xx-rewrite code

5 files changed, 91 insertions, 190 deletions

diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
index 851b488433..abb023c7de 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
@@ -16,85 +16,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
 		       const char *function,
 		       int line);
 
-#define RADEON_CP_PACKET3_NOP                       0xC0001000
-#define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
-#define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
-#define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
-#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
-#define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
-#define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
-#define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
-#define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
-#define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
-#define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
-#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
-#define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
-#define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
-#define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
-#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
-#define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
-#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
-#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
-#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
-#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
-
-/* r6xx/r7xx packet 3 type offsets */
-#define R600_SET_CONFIG_REG_OFFSET                  0x00008000
-#define R600_SET_CONFIG_REG_END                     0x0000ac00
-#define R600_SET_CONTEXT_REG_OFFSET                 0x00028000
-#define R600_SET_CONTEXT_REG_END                    0x00029000
-#define R600_SET_ALU_CONST_OFFSET                   0x00030000
-#define R600_SET_ALU_CONST_END                      0x00032000
-#define R600_SET_RESOURCE_OFFSET                    0x00038000
-#define R600_SET_RESOURCE_END                       0x0003c000
-#define R600_SET_SAMPLER_OFFSET                     0x0003c000
-#define R600_SET_SAMPLER_END                        0x0003cff0
-#define R600_SET_CTL_CONST_OFFSET                   0x0003cff0
-#define R600_SET_CTL_CONST_END                      0x0003e200
-#define R600_SET_LOOP_CONST_OFFSET                  0x0003e200
-#define R600_SET_LOOP_CONST_END                     0x0003e380
-#define R600_SET_BOOL_CONST_OFFSET                  0x0003e380
-#define R600_SET_BOOL_CONST_END                     0x00040000
-
-/* r6xx/r7xx packet 3 types */
-#define R600_IT_INDIRECT_BUFFER_END               0x00001700
-#define R600_IT_SET_PREDICATION                   0x00002000
-#define R600_IT_REG_RMW                           0x00002100
-#define R600_IT_COND_EXEC                         0x00002200
-#define R600_IT_PRED_EXEC                         0x00002300
-#define R600_IT_START_3D_CMDBUF                   0x00002400
-#define R600_IT_DRAW_INDEX_2                      0x00002700
-#define R600_IT_CONTEXT_CONTROL                   0x00002800
-#define R600_IT_DRAW_INDEX_IMMD_BE                0x00002900
-#define R600_IT_INDEX_TYPE                        0x00002A00
-#define R600_IT_DRAW_INDEX                        0x00002B00
-#define R600_IT_DRAW_INDEX_AUTO                   0x00002D00
-#define R600_IT_DRAW_INDEX_IMMD                   0x00002E00
-#define R600_IT_NUM_INSTANCES                     0x00002F00
-#define R600_IT_STRMOUT_BUFFER_UPDATE             0x00003400
-#define R600_IT_INDIRECT_BUFFER_MP                0x00003800
-#define R600_IT_MEM_SEMAPHORE                     0x00003900
-#define R600_IT_MPEG_INDEX                        0x00003A00
-#define R600_IT_WAIT_REG_MEM                      0x00003C00
-#define R600_IT_MEM_WRITE                         0x00003D00
-#define R600_IT_INDIRECT_BUFFER                   0x00003200
-#define R600_IT_CP_INTERRUPT                      0x00004000
-#define R600_IT_SURFACE_SYNC                      0x00004300
-#define R600_IT_ME_INITIALIZE                     0x00004400
-#define R600_IT_COND_WRITE                        0x00004500
-#define R600_IT_EVENT_WRITE                       0x00004600
-#define R600_IT_EVENT_WRITE_EOP                   0x00004700
-#define R600_IT_ONE_REG_WRITE                     0x00005700
-#define R600_IT_SET_CONFIG_REG                    0x00006800
-#define R600_IT_SET_CONTEXT_REG                   0x00006900
-#define R600_IT_SET_ALU_CONST                     0x00006A00
-#define R600_IT_SET_BOOL_CONST                    0x00006B00
-#define R600_IT_SET_LOOP_CONST                    0x00006C00
-#define R600_IT_SET_RESOURCE                      0x00006D00
-#define R600_IT_SET_SAMPLER                       0x00006E00
-#define R600_IT_SET_CTL_CONST                     0x00006F00
-#define R600_IT_SURFACE_BASE_UPDATE               0x00007300
-
+/* +r6/r7 : code here moved */
 
 #define CP_PACKET2  (2 << 30)
 #define CP_PACKET0(reg, n)	(RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
@@ -188,54 +110,14 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
 #define OUT_BATCH_FLOAT32(f) \
 	OUT_BATCH(radeonPackFloat32((f)))
 
-/* R600/R700 */
-#define R600_OUT_BATCH_REGS(reg, num)					\
-do {								\
-	if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2);	\
-	} else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
-		OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)));	\
-		OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2);	\
-	} else {							\
-		OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (num))); \
-	}								\
-} while (0)
-
-/** Single register write to command buffer; requires 3 dwords for most things. */
-#define R600_OUT_BATCH_REGVAL(reg, val)		\
-	R600_OUT_BATCH_REGS((reg), 1);		\
-	OUT_BATCH((val))
-
-/** Continuous register range write to command buffer; requires 1 dword,
- * expects count dwords afterwards for register contents. */
-#define R600_OUT_BATCH_REGSEQ(reg, count)	\
-	R600_OUT_BATCH_REGS((reg), (count))
+/* +r6/r7 : code here moved */
 
 /* Fire the buffered vertices no matter what.
  */
 static INLINE void radeon_firevertices(radeonContextPtr radeon)
 {
    if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
-      radeonFlush(radeon->glCtx);
+      radeon->glCtx->Driver.Flush(radeon->glCtx); /* +r6/r7 */
 }
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 756c09fff3..691615938f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -914,7 +914,7 @@ again:
 	if (ret == RADEON_CS_SPACE_OP_TO_BIG)
 		return GL_FALSE;
 	if (ret == RADEON_CS_SPACE_FLUSH) {
-		radeonFlush(ctx);
+		ctx->Driver.Flush(ctx); /* +r6/r7 */
 		if (flushed)
 			return GL_FALSE;
 		flushed = 1;
@@ -1014,7 +1014,7 @@ void radeonFinish(GLcontext * ctx)
 	struct gl_framebuffer *fb = ctx->DrawBuffer;
 	int i;
 
-	radeonFlush(ctx);
+	ctx->Driver.Flush(ctx); /* +r6/r7 */
 
 	if (radeon->radeonScreen->kernel_mm) {
 		for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
index b47b095cf2..b33417e93e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
@@ -216,22 +216,28 @@ static int cs_process_relocs(struct radeon_cs *cs)
 
     csm = (struct cs_manager_legacy*)cs->csm;
     relocs = (struct cs_reloc_legacy *)cs->relocs;
- restart:
-    for (i = 0; i < cs->crelocs; i++) {
-        for (j = 0; j < relocs[i].cindices; j++) {
+restart:
+    for (i = 0; i < cs->crelocs; i++) 
+    {
+        for (j = 0; j < relocs[i].cindices; j++) 
+        {
             uint32_t soffset, eoffset;
 
             r = radeon_bo_legacy_validate(relocs[i].base.bo,
                                            &soffset, &eoffset);
-	    if (r == -EAGAIN)
-	      goto restart;
-            if (r) {
+	        if (r == -EAGAIN)
+            {
+	             goto restart;
+            }
+            if (r) 
+            {
                 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
                         relocs[i].base.bo, soffset, eoffset);
                 return r;
             }
             cs->packets[relocs[i].indices[j]] += soffset;
-            if (cs->packets[relocs[i].indices[j]] >= eoffset) {
+            if (cs->packets[relocs[i].indices[j]] >= eoffset) 
+            {
 	      /*                radeon_bo_debug(relocs[i].base.bo, 12); */
                 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
                         relocs[i].base.bo, soffset, eoffset);
@@ -280,7 +286,8 @@ static int cs_emit(struct radeon_cs *cs)
     csm->ctx->vtbl.emit_cs_header(cs, csm->ctx);
 
     /* append buffer age */
-    if (IS_R300_CLASS(csm->ctx->radeonScreen)) {
+    if ( IS_R300_CLASS(csm->ctx->radeonScreen) )
+    { 
       age.scratch.cmd_type = R300_CMD_SCRATCH;
       /* Scratch register 2 corresponds to what radeonGetAge polls */
       csm->pending_age = 0;
@@ -315,7 +322,8 @@ static int cs_emit(struct radeon_cs *cs)
     if (r) {
         return r;
     }
-    if (!IS_R300_CLASS(csm->ctx->radeonScreen)) {
+    if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) &&
+        (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */
 	drm_radeon_irq_emit_t emit_cmd;
 	emit_cmd.irq_seq = &csm->pending_age;
 	r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));
@@ -387,59 +395,71 @@ static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bo
         return 0;
 
     /* prepare */
-    for (i = 0; i < num_bo; i++) {
-      bo = bos[i].bo;
-
-      bos[i].new_accounted = 0;
-      read_domains = bos[i].read_domains;
-      write_domain = bos[i].write_domain;
-		
-      /* pinned bos don't count */
-      if (radeon_legacy_bo_is_static(bo))
-	  continue;
+    for (i = 0; i < num_bo; i++) 
+    {
+         bo = bos[i].bo;
+
+         bos[i].new_accounted = 0;
+         read_domains = bos[i].read_domains;
+         write_domain = bos[i].write_domain;
+		   
+         /* pinned bos don't count */
+         if (radeon_legacy_bo_is_static(bo))
+	     continue;
  
-      /* already accounted this bo */
-      if (write_domain && (write_domain == bo->space_accounted))
-	  continue;
+         /* already accounted this bo */
+         if (write_domain && (write_domain == bo->space_accounted))
+	     continue;
 
-      if (read_domains && ((read_domains << 16) == bo->space_accounted))
-	  continue;
+         if (read_domains && ((read_domains << 16) == bo->space_accounted))
+	     continue;
       
-      if (bo->space_accounted == 0) {
-	  if (write_domain == RADEON_GEM_DOMAIN_VRAM)
-	      this_op_vram_write += bo->size;
-	  else if (write_domain == RADEON_GEM_DOMAIN_GTT)
-	      this_op_gart_write += bo->size;
-	  else
-	      this_op_read += bo->size;
-	  bos[i].new_accounted = (read_domains << 16) | write_domain;
-      } else {
-	  uint16_t old_read, old_write;
-	  
-	  old_read = bo->space_accounted >> 16;
-	  old_write = bo->space_accounted & 0xffff;
-
-	  if (write_domain && (old_read & write_domain)) {
-	      bos[i].new_accounted = write_domain;
-	      /* moving from read to a write domain */
-	      if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
-		  this_op_read -= bo->size;
-		  this_op_vram_write += bo->size;
-	      } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
-		  this_op_read -= bo->size;
-		  this_op_gart_write += bo->size;
-	      }
-	  } else if (read_domains & old_write) {
-	      bos[i].new_accounted = bo->space_accounted & 0xffff;
-	  } else {
-	      /* rewrite the domains */
-	      if (write_domain != old_write)
-		  fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
-	      if (read_domains != old_read)
-		  fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
-	      return RADEON_CS_SPACE_FLUSH;
-	  }
-      }
+         if (bo->space_accounted == 0) 
+         {
+	         if (write_domain == RADEON_GEM_DOMAIN_VRAM)
+	             this_op_vram_write += bo->size;
+	         else if (write_domain == RADEON_GEM_DOMAIN_GTT)
+	             this_op_gart_write += bo->size;
+	         else
+	             this_op_read += bo->size;
+	         bos[i].new_accounted = (read_domains << 16) | write_domain;
+         } 
+         else 
+         {
+	        uint16_t old_read, old_write;
+	     
+	        old_read = bo->space_accounted >> 16;
+	        old_write = bo->space_accounted & 0xffff;
+
+	        if (write_domain && (old_read & write_domain)) 
+            {
+	            bos[i].new_accounted = write_domain;
+	            /* moving from read to a write domain */
+	            if (write_domain == RADEON_GEM_DOMAIN_VRAM) 
+                {
+		            this_op_read -= bo->size;
+		            this_op_vram_write += bo->size;
+	            } 
+                else if (write_domain == RADEON_GEM_DOMAIN_VRAM) 
+                {
+		            this_op_read -= bo->size;
+		            this_op_gart_write += bo->size;
+	            }
+	        } 
+            else if (read_domains & old_write) 
+            {
+	            bos[i].new_accounted = bo->space_accounted & 0xffff;
+	        } 
+            else 
+            {
+	            /* rewrite the domains */
+	            if (write_domain != old_write)
+		            fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
+	            if (read_domains != old_read)
+		            fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
+	            return RADEON_CS_SPACE_FLUSH;
+	        }
+         }
 	}
 	
 	if (this_op_read < 0)
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index f62ca7f9eb..b2585eae77 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -165,7 +165,7 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
       return GL_FALSE;
    }
 
-  radeonFlush(ctx);
+  ctx->Driver.Flush(ctx); /* +r6/r7 */
 
   if (rrb->bo)
     radeon_bo_unref(rrb->bo);
@@ -371,7 +371,7 @@ radeon_framebuffer_renderbuffer(GLcontext * ctx,
                                GLenum attachment, struct gl_renderbuffer *rb)
 {
 
-   radeonFlush(ctx);
+   ctx->Driver.Flush(ctx); /* +r6/r7 */
 
    _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb);
    radeon_draw_buffer(ctx, fb);
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index b75db5b80c..be3b816b86 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -61,8 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_tex.h"
 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
 #include "r600_context.h"
-#include "r700_fragprog.h"
-#include "r700_tex.h"
+//#include "r700_driconf.h" /* +r6/r7 */
+#include "r700_tex.h"     /* +r6/r7 */
 #endif
 
 #include "utils.h"
@@ -405,13 +405,13 @@ static const __DRItexBufferExtension r300TexBufferExtension = {
 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
 static const __DRItexOffsetExtension r600texOffsetExtension = {
     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
-   r700SetTexOffset,
+   r700SetTexOffset, /* +r6/r7 */
 };
 
 static const __DRItexBufferExtension r600TexBufferExtension = {
     { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
-   r700SetTexBuffer,
-   r700SetTexBuffer2,
+   r700SetTexBuffer,  /* +r6/r7 */
+   r700SetTexBuffer2, /* +r6/r7 */
 };
 #endif
 
@@ -941,7 +941,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
 #endif
-
    /* parse information in __driConfigOptions */
    driParseOptionInfo (&screen->optionCache,
 		       __driConfigOptions, __driNConfigOptions);