diff options
| author | Roland Scheidegger <rscheidegger@gmx.ch> | 2005-02-10 21:59:20 +0000 |
|---|---|---|
| committer | Roland Scheidegger <rscheidegger@gmx.ch> | 2005-02-10 21:59:20 +0000 |
| commit | 26d31591257d575362776972439f614948366dd1 (patch) | |
| tree | 209562286e1c790f8b324c33c418fad2d5862db6 /src/mesa/drivers/dri/radeon | |
| parent | b66251f76da2e2b0419bc1fbaec4dd0c9f8867b2 (diff) | |
add the new RADEON_CUBIC_OFFSET/FACES state packets/registers to radeon (and r200) sanity code
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_sanity.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c index 3a3bbb78bd..f5de2758ac 100644 --- a/src/mesa/drivers/dri/radeon/radeon_sanity.c +++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c @@ -140,7 +140,12 @@ static struct { { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, { 0, 3, "R200_RB3D_BLENDCOLOR" }, { 0, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, - + { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" }, + { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" }, + { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" }, + { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" }, + { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" }, + { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" }, }; struct reg_names { @@ -234,6 +239,24 @@ static struct reg_names reg_names[] = { { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" }, { RADEON_PP_TEX_SIZE_1+4, "RADEON_PP_TEX_PITCH_1" }, { RADEON_PP_TEX_SIZE_2+4, "RADEON_PP_TEX_PITCH_2" }, + { RADEON_PP_CUBIC_FACES_0, "RADEON_PP_CUBIC_FACES_0" }, + { RADEON_PP_CUBIC_FACES_1, "RADEON_PP_CUBIC_FACES_1" }, + { RADEON_PP_CUBIC_FACES_2, "RADEON_PP_CUBIC_FACES_2" }, + { RADEON_PP_CUBIC_OFFSET_T0_0, "RADEON_PP_CUBIC_OFFSET_T0_0" }, + { RADEON_PP_CUBIC_OFFSET_T0_1, "RADEON_PP_CUBIC_OFFSET_T0_1" }, + { RADEON_PP_CUBIC_OFFSET_T0_2, "RADEON_PP_CUBIC_OFFSET_T0_2" }, + { RADEON_PP_CUBIC_OFFSET_T0_3, "RADEON_PP_CUBIC_OFFSET_T0_3" }, + { RADEON_PP_CUBIC_OFFSET_T0_4, "RADEON_PP_CUBIC_OFFSET_T0_4" }, + { RADEON_PP_CUBIC_OFFSET_T1_0, "RADEON_PP_CUBIC_OFFSET_T1_0" }, + { RADEON_PP_CUBIC_OFFSET_T1_1, "RADEON_PP_CUBIC_OFFSET_T1_1" }, + { RADEON_PP_CUBIC_OFFSET_T1_2, "RADEON_PP_CUBIC_OFFSET_T1_2" }, + { RADEON_PP_CUBIC_OFFSET_T1_3, "RADEON_PP_CUBIC_OFFSET_T1_3" }, + { RADEON_PP_CUBIC_OFFSET_T1_4, "RADEON_PP_CUBIC_OFFSET_T1_4" }, + { RADEON_PP_CUBIC_OFFSET_T2_0, "RADEON_PP_CUBIC_OFFSET_T2_0" }, + { RADEON_PP_CUBIC_OFFSET_T2_1, "RADEON_PP_CUBIC_OFFSET_T2_1" }, + { RADEON_PP_CUBIC_OFFSET_T2_2, "RADEON_PP_CUBIC_OFFSET_T2_2" }, + { RADEON_PP_CUBIC_OFFSET_T2_3, "RADEON_PP_CUBIC_OFFSET_T2_3" }, + { RADEON_PP_CUBIC_OFFSET_T2_4, "RADEON_PP_CUBIC_OFFSET_T2_4" }, }; static struct reg_names scalar_names[] = { |