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authorAlex Deucher <alexdeucher@gmail.com>2010-03-03 16:12:22 -0500
committerAlex Deucher <alexdeucher@gmail.com>2010-03-03 16:14:17 -0500
commit3594bf233d16ceb21e97fcdfb57ea45cb0c5e41b (patch)
tree0311e41747d16d7c13b169f473090047cdaa9c4b /src/mesa/drivers/dri/radeon
parent21cc53c2bc1dbd2ddd8510f68215497ed3c2088e (diff)
radeon/r200/r300/r600: add check_blit vtbl function
Check if the native blit formats are supported, if not, attempt to use an alternate format. Skip 3, >4 bpp as per comments from mcencora on irc. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_blit.c4
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_blit.h2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common_context.h1
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.c1
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_tex_copy.c44
5 files changed, 45 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c
index 34b9af4063..e188a122d5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.c
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.c
@@ -38,7 +38,7 @@ static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
}
/* common formats supported as both textures and render targets */
-static unsigned is_blit_supported(gl_format mesa_format)
+unsigned r100_check_blit(gl_format mesa_format)
{
/* XXX others? BE/LE? */
switch (mesa_format) {
@@ -333,7 +333,7 @@ unsigned r100_blit(GLcontext *ctx,
{
struct r100_context *r100 = R100_CONTEXT(ctx);
- if (!is_blit_supported(dst_mesaformat))
+ if (!r100_check_blit(dst_mesaformat))
return GL_FALSE;
/* Make sure that colorbuffer has even width - hw limitation */
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.h b/src/mesa/drivers/dri/radeon/radeon_blit.h
index d36366ff79..d7d0b5554a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.h
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.h
@@ -30,6 +30,8 @@
void r100_blit_init(struct r100_context *r100);
+unsigned r100_check_blit(gl_format mesa_format);
+
unsigned r100_blit(GLcontext *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index e397ee8c22..d1a24e265f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -518,6 +518,7 @@ struct radeon_context {
void (*free_context)(GLcontext *ctx);
void (*emit_query_finish)(radeonContextPtr radeon);
void (*update_scissor)(GLcontext *ctx);
+ unsigned (*check_blit)(gl_format mesa_format);
unsigned (*blit)(GLcontext *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index 4625af14ad..878a453bd5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -198,6 +198,7 @@ static void r100_init_vtbl(radeonContextPtr radeon)
radeon->vtbl.fallback = radeonFallback;
radeon->vtbl.free_context = r100_vtbl_free_context;
radeon->vtbl.emit_query_finish = r100_emit_query_finish;
+ radeon->vtbl.check_blit = r100_check_blit;
radeon->vtbl.blit = r100_blit;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
index 18cf182e54..89fe9915a7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
@@ -46,6 +46,12 @@ do_copy_texsubimage(GLcontext *ctx,
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
+ unsigned src_bpp;
+ unsigned dst_bpp;
+ gl_format src_mesaformat;
+ gl_format dst_mesaformat;
+ unsigned src_width;
+ unsigned dst_width;
if (_mesa_get_format_bits(timg->base.TexFormat, GL_DEPTH_BITS) > 0) {
rrb = radeon_get_depthbuffer(radeon);
@@ -76,12 +82,40 @@ do_copy_texsubimage(GLcontext *ctx,
}
+ src_mesaformat = rrb->base.Format;
+ dst_mesaformat = timg->base.TexFormat;
+ src_width = rrb->base.Width;
+ dst_width = timg->base.Width;
+ src_bpp = _mesa_get_format_bytes(src_mesaformat);
+ dst_bpp = _mesa_get_format_bytes(dst_mesaformat);
+ if (!radeon->vtbl.check_blit(dst_mesaformat)) {
+ if (src_bpp != dst_bpp)
+ return GL_FALSE;
+
+ switch (dst_bpp) {
+ case 2:
+ src_mesaformat = MESA_FORMAT_RGB565;
+ dst_mesaformat = MESA_FORMAT_RGB565;
+ break;
+ case 4:
+ src_mesaformat = MESA_FORMAT_ARGB8888;
+ dst_mesaformat = MESA_FORMAT_ARGB8888;
+ break;
+ case 1:
+ src_mesaformat = MESA_FORMAT_A8;
+ dst_mesaformat = MESA_FORMAT_A8;
+ break;
+ default:
+ return GL_FALSE;
+ }
+ }
+
/* blit from src buffer to texture */
- return radeon->vtbl.blit(ctx, rrb->bo, src_offset, rrb->base.Format, rrb->pitch/rrb->cpp,
- rrb->base.Width, rrb->base.Height, x, y,
- timg->mt->bo, dst_offset, timg->base.TexFormat,
- timg->mt->levels[level].rowstride / _mesa_get_format_bytes(timg->base.TexFormat),
- timg->base.Width, timg->base.Height,
+ return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp,
+ src_width, rrb->base.Height, x, y,
+ timg->mt->bo, dst_offset, dst_mesaformat,
+ timg->mt->levels[level].rowstride / dst_bpp,
+ dst_width, timg->base.Height,
dstx, dsty, width, height, 1);
}