diff options
author | Brian Paul <brianp@vmware.com> | 2009-01-28 14:45:18 -0700 |
---|---|---|
committer | Brian Paul <brianp@vmware.com> | 2009-01-28 14:45:18 -0700 |
commit | 68acc61fc3dd110949f26af01ef5943e6de85ec7 (patch) | |
tree | d6843c9d6d4c2ea72250f7dc1395875b4036c909 /src/mesa/drivers/dri | |
parent | 89fddf978c9d2ab5042f89110015234e979c2686 (diff) | |
parent | faa48915d27634a12f123eaa6e954ec79565e365 (diff) |
Merge commit 'origin/master' into texture_swizzle
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_structs.h | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.h | 9 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_pass0.c | 21 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_fbo.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_fbo.h | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_span.c | 9 |
6 files changed, 26 insertions, 22 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 4e577d0f6a..d97ff27f0a 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1031,10 +1031,10 @@ struct brw_surface_state GLuint writedisable_green:1; GLuint writedisable_red:1; GLuint writedisable_alpha:1; - GLuint surface_format:9; + GLuint surface_format:9; /**< BRW_SURFACEFORMAT_x */ GLuint data_return_format:1; GLuint pad0:1; - GLuint surface_type:3; + GLuint surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ } ss0; struct { diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index ded079695e..388c6f7618 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -60,16 +60,15 @@ struct brw_wm_prog_key { GLuint aa_dest_stencil_reg:3; GLuint dest_depth_reg:3; GLuint nr_depth_regs:3; - GLuint projtex_mask:8; - GLuint shadowtex_mask:8; GLuint computes_depth:1; /* could be derived from program string */ GLuint source_depth_to_render_target:1; GLuint flat_shade:1; GLuint runtime_check_aads_emit:1; - GLuint yuvtex_mask:8; - GLuint yuvtex_swap_mask:8; /* UV swaped */ - GLuint pad1:16; + GLuint projtex_mask:16; + GLuint shadowtex_mask:16; + GLuint yuvtex_mask:16; + GLuint yuvtex_swap_mask:16; /* UV swaped */ GLuint program_string_id:32; GLuint origin_x, origin_y; diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass0.c b/src/mesa/drivers/dri/i965/brw_wm_pass0.c index d0c6b82290..590cd946ec 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass0.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass0.c @@ -51,6 +51,7 @@ static struct brw_wm_value *get_value( struct brw_wm_compile *c) return &c->vreg[c->nr_vreg++]; } +/** return pointer to a newly allocated instruction */ static struct brw_wm_instruction *get_instruction( struct brw_wm_compile *c ) { assert(c->nr_insns < BRW_WM_MAX_INSN); @@ -60,6 +61,7 @@ static struct brw_wm_instruction *get_instruction( struct brw_wm_compile *c ) /*********************************************************************** */ +/** Init the "undef" register */ static void pass0_init_undef( struct brw_wm_compile *c) { struct brw_wm_ref *ref = &c->undef_ref; @@ -69,6 +71,7 @@ static void pass0_init_undef( struct brw_wm_compile *c) ref->prevuse = NULL; } +/** Set a FP register to a value */ static void pass0_set_fpreg_value( struct brw_wm_compile *c, GLuint file, GLuint idx, @@ -83,6 +86,7 @@ static void pass0_set_fpreg_value( struct brw_wm_compile *c, c->pass0_fp_reg[file][idx][component] = ref; } +/** Set a FP register to a ref */ static void pass0_set_fpreg_ref( struct brw_wm_compile *c, GLuint file, GLuint idx, @@ -121,6 +125,7 @@ static const struct brw_wm_ref *get_param_ref( struct brw_wm_compile *c, } +/** Return a ref to a constant/literal value */ static const struct brw_wm_ref *get_const_ref( struct brw_wm_compile *c, const GLfloat *constval ) { @@ -187,7 +192,7 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c, /* There's something really hokey about parameters parsed in * arb programs - they all end up in here, whether they be - * state values, paramters or constants. This duplicates the + * state values, parameters or constants. This duplicates the * structure above & also seems to subvert the limits set for * each type of constant/param. */ @@ -374,14 +379,22 @@ static void pass0_precalc_mov( struct brw_wm_compile *c, { const struct prog_dst_register *dst = &inst->DstReg; GLuint writemask = inst->DstReg.WriteMask; + struct brw_wm_ref *refs[4]; GLuint i; /* Get the effect of a MOV by manipulating our register table: + * First get all refs, then assign refs. This ensures that "in-place" + * swizzles such as: + * MOV t, t.xxyx + * are handled correctly. Previously, these two steps were done in + * one loop and the above case was incorrectly handled. */ for (i = 0; i < 4; i++) { - if (writemask & (1<<i)) { - pass0_set_fpreg_ref( c, dst->File, dst->Index, i, - get_new_ref(c, inst->SrcReg[0], i, NULL)); + refs[i] = get_new_ref(c, inst->SrcReg[0], i, NULL); + } + for (i = 0; i < 4; i++) { + if (writemask & (1 << i)) { + pass0_set_fpreg_ref( c, dst->File, dst->Index, i, refs[i]); } } } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 05847ee5fe..53a74f5c0b 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -290,8 +290,6 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb, rb->region = NULL; intel_region_reference(&rb->region, region); intel_region_release(&old); - - rb->pfPitch = region->pitch; } /** diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index a44989b5fd..41ced2a01a 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -63,11 +63,8 @@ struct intel_renderbuffer { struct gl_renderbuffer Base; struct intel_region *region; - GLuint pfPitch; /* possibly paged flipped pitch */ GLboolean RenderToTexture; /* RTT? */ - GLuint pf_pending; /**< sequence number of pending flip */ - GLuint vbl_pending; /**< vblank sequence number of pending flip */ uint8_t *span_cache; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index d9315043e6..c990caf3eb 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -150,7 +150,7 @@ static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb, int x_tile_number, y_tile_number; int tile_off, tile_base; - tile_stride = (irb->pfPitch * irb->region->cpp) << 3; + tile_stride = (irb->region->pitch * irb->region->cpp) << 3; xbyte = x * irb->region->cpp; @@ -190,7 +190,7 @@ static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb, printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n", x, y, tile_off, tile_base, tile_off + tile_base, - irb->pfPitch, tile_stride); + irb->region->pitch, tile_stride); #endif return tile_base + tile_off; @@ -205,7 +205,7 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, int x_tile_number, y_tile_number; int tile_off, tile_base; - tile_stride = (irb->pfPitch * irb->region->cpp) << 5; + tile_stride = (irb->region->pitch * irb->region->cpp) << 5; xbyte = x * irb->region->cpp; @@ -528,8 +528,6 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb) if (irb == NULL || irb->region == NULL) return; - irb->pfPitch = irb->region->pitch; - intel_set_span_functions(intel, rb); } @@ -543,7 +541,6 @@ intel_renderbuffer_unmap(struct intel_context *intel, return; clear_span_cache(irb); - irb->pfPitch = 0; rb->GetRow = NULL; rb->PutRow = NULL; |