Merge branch 'master' into r300-compiler

There were additional non-textual conflicts. Conflicts: src/gallium/drivers/r300/r300_tgsi_to_rc.c src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c src/mesa/drivers/dri/r300/compiler/radeon_program.c src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
author: Nicolai Hähnle <nhaehnle@gmail.com> 2009-09-21 13:26:50 +0200
committer: Nicolai Hähnle <nhaehnle@gmail.com> 2009-09-21 13:26:50 +0200
commit: 81c7561d9d3faf70ac22c6a5f3fbea18f53eed92 (patch)
tree: 5ec097e0e1fe99804104d3a56923c16edf1533aa /src/mesa/drivers/dri
parent: f02f63997ce65530788a6dfcb28f11790a14d938 (diff)
parent: 3083ba38f4c884b32cd0460607b5064b6b7008d2 (diff)
70 files changed, 1125 insertions, 716 deletions
diff --git a/src/mesa/drivers/dri/common/extension_helper.h b/src/mesa/drivers/dri/common/extension_helper.h
index 40a030ce0d..5e86324eec 100644
--- a/src/mesa/drivers/dri/common/extension_helper.h
+++ b/src/mesa/drivers/dri/common/extension_helper.h
@@ -316,6 +316,13 @@ static const char CombinerOutputNV_names[] =
     "";
 #endif
 
+#if defined(need_GL_NV_vertex_program)
+static const char VertexAttribs3fvNV_names[] =
+    "iip\0" /* Parameter signature */
+    "glVertexAttribs3fvNV\0"
+    "";
+#endif
+
 #if defined(need_GL_VERSION_2_0) || defined(need_GL_ARB_shader_objects)
 static const char Uniform2fARB_names[] =
     "iff\0" /* Parameter signature */
@@ -575,6 +582,13 @@ static const char MatrixIndexusvARB_names[] =
     "";
 #endif
 
+#if defined(need_GL_ARB_draw_elements_base_vertex)
+static const char DrawElementsBaseVertex_names[] =
+    "iiipi\0" /* Parameter signature */
+    "glDrawElementsBaseVertex\0"
+    "";
+#endif
+
 #if defined(need_GL_VERSION_2_0) || defined(need_GL_ARB_vertex_program)
 static const char DisableVertexAttribArrayARB_names[] =
     "i\0" /* Parameter signature */
@@ -970,10 +984,10 @@ static const char GlobalAlphaFactordSUN_names[] =
     "";
 #endif
 
-#if defined(need_GL_NV_vertex_program)
-static const char VertexAttribs3fvNV_names[] =
+#if defined(need_GL_NV_register_combiners)
+static const char GetFinalCombinerInputParameterfvNV_names[] =
     "iip\0" /* Parameter signature */
-    "glVertexAttribs3fvNV\0"
+    "glGetFinalCombinerInputParameterfvNV\0"
     "";
 #endif
 
@@ -3918,6 +3932,13 @@ static const char MapBufferARB_names[] =
     "";
 #endif
 
+#if defined(need_GL_ARB_draw_elements_base_vertex)
+static const char MultiDrawElementsBaseVertex_names[] =
+    "ipipip\0" /* Parameter signature */
+    "glMultiDrawElementsBaseVertex\0"
+    "";
+#endif
+
 #if defined(need_GL_EXT_coordinate_frame)
 static const char Binormal3svEXT_names[] =
     "p\0" /* Parameter signature */
@@ -4396,10 +4417,11 @@ static const char SpriteParameterivSGIX_names[] =
     "";
 #endif
 
-#if defined(need_GL_EXT_provoking_vertex)
+#if defined(need_GL_EXT_provoking_vertex) || defined(need_GL_ARB_provoking_vertex)
 static const char ProvokingVertexEXT_names[] =
     "i\0" /* Parameter signature */
     "glProvokingVertexEXT\0"
+    "glProvokingVertex\0"
     "";
 #endif
 
@@ -4554,10 +4576,10 @@ static const char UniformMatrix3x4fv_names[] =
     "";
 #endif
 
-#if defined(need_GL_EXT_coordinate_frame)
-static const char Binormal3fvEXT_names[] =
-    "p\0" /* Parameter signature */
-    "glBinormal3fvEXT\0"
+#if defined(need_GL_ARB_draw_elements_base_vertex)
+static const char DrawRangeElementsBaseVertex_names[] =
+    "iiiiipi\0" /* Parameter signature */
+    "glDrawRangeElementsBaseVertex\0"
     "";
 #endif
 
@@ -4710,10 +4732,10 @@ static const char GetFragmentLightfvSGIX_names[] =
     "";
 #endif
 
-#if defined(need_GL_NV_register_combiners)
-static const char GetFinalCombinerInputParameterfvNV_names[] =
-    "iip\0" /* Parameter signature */
-    "glGetFinalCombinerInputParameterfvNV\0"
+#if defined(need_GL_EXT_coordinate_frame)
+static const char Binormal3fvEXT_names[] =
+    "p\0" /* Parameter signature */
+    "glBinormal3fvEXT\0"
     "";
 #endif
 
@@ -5090,6 +5112,15 @@ static const struct dri_extension_function GL_ARB_draw_buffers_functions[] = {
 };
 #endif
 
+#if defined(need_GL_ARB_draw_elements_base_vertex)
+static const struct dri_extension_function GL_ARB_draw_elements_base_vertex_functions[] = {
+    { DrawElementsBaseVertex_names, DrawElementsBaseVertex_remap_index, -1 },
+    { MultiDrawElementsBaseVertex_names, MultiDrawElementsBaseVertex_remap_index, -1 },
+    { DrawRangeElementsBaseVertex_names, DrawRangeElementsBaseVertex_remap_index, -1 },
+    { NULL, 0, 0 }
+};
+#endif
+
 #if defined(need_GL_ARB_framebuffer_object)
 static const struct dri_extension_function GL_ARB_framebuffer_object_functions[] = {
     { BlitFramebufferEXT_names, BlitFramebufferEXT_remap_index, -1 },
@@ -5164,6 +5195,13 @@ static const struct dri_extension_function GL_ARB_point_parameters_functions[] =
 };
 #endif
 
+#if defined(need_GL_ARB_provoking_vertex)
+static const struct dri_extension_function GL_ARB_provoking_vertex_functions[] = {
+    { ProvokingVertexEXT_names, ProvokingVertexEXT_remap_index, -1 },
+    { NULL, 0, 0 }
+};
+#endif
+
 #if defined(need_GL_ARB_shader_objects)
 static const struct dri_extension_function GL_ARB_shader_objects_functions[] = {
     { UniformMatrix3fvARB_names, UniformMatrix3fvARB_remap_index, -1 },
@@ -5520,8 +5558,8 @@ static const struct dri_extension_function GL_EXT_coordinate_frame_functions[] =
     { Binormal3dvEXT_names, Binormal3dvEXT_remap_index, -1 },
     { Tangent3iEXT_names, Tangent3iEXT_remap_index, -1 },
     { Tangent3bvEXT_names, Tangent3bvEXT_remap_index, -1 },
-    { Binormal3fvEXT_names, Binormal3fvEXT_remap_index, -1 },
     { Tangent3bEXT_names, Tangent3bEXT_remap_index, -1 },
+    { Binormal3fvEXT_names, Binormal3fvEXT_remap_index, -1 },
     { BinormalPointerEXT_names, BinormalPointerEXT_remap_index, -1 },
     { Tangent3svEXT_names, Tangent3svEXT_remap_index, -1 },
     { Binormal3bEXT_names, Binormal3bEXT_remap_index, -1 },
@@ -5963,6 +6001,7 @@ static const struct dri_extension_function GL_NV_point_sprite_functions[] = {
 static const struct dri_extension_function GL_NV_register_combiners_functions[] = {
     { CombinerOutputNV_names, CombinerOutputNV_remap_index, -1 },
     { CombinerParameterfvNV_names, CombinerParameterfvNV_remap_index, -1 },
+    { GetFinalCombinerInputParameterfvNV_names, GetFinalCombinerInputParameterfvNV_remap_index, -1 },
     { GetCombinerOutputParameterfvNV_names, GetCombinerOutputParameterfvNV_remap_index, -1 },
     { FinalCombinerInputNV_names, FinalCombinerInputNV_remap_index, -1 },
     { GetCombinerInputParameterfvNV_names, GetCombinerInputParameterfvNV_remap_index, -1 },
@@ -5971,7 +6010,6 @@ static const struct dri_extension_function GL_NV_register_combiners_functions[]
     { GetFinalCombinerInputParameterivNV_names, GetFinalCombinerInputParameterivNV_remap_index, -1 },
     { CombinerInputNV_names, CombinerInputNV_remap_index, -1 },
     { CombinerParameterfNV_names, CombinerParameterfNV_remap_index, -1 },
-    { GetFinalCombinerInputParameterfvNV_names, GetFinalCombinerInputParameterfvNV_remap_index, -1 },
     { GetCombinerInputParameterivNV_names, GetCombinerInputParameterivNV_remap_index, -1 },
     { CombinerParameterivNV_names, CombinerParameterivNV_remap_index, -1 },
     { NULL, 0, 0 }
@@ -5998,6 +6036,7 @@ static const struct dri_extension_function GL_NV_vertex_array_range_functions[]
 static const struct dri_extension_function GL_NV_vertex_program_functions[] = {
     { VertexAttrib4ubvNV_names, VertexAttrib4ubvNV_remap_index, -1 },
     { VertexAttrib4svNV_names, VertexAttrib4svNV_remap_index, -1 },
+    { VertexAttribs3fvNV_names, VertexAttribs3fvNV_remap_index, -1 },
     { VertexAttribs1dvNV_names, VertexAttribs1dvNV_remap_index, -1 },
     { VertexAttrib1fvNV_names, VertexAttrib1fvNV_remap_index, -1 },
     { VertexAttrib4fNV_names, VertexAttrib4fNV_remap_index, -1 },
@@ -6006,7 +6045,6 @@ static const struct dri_extension_function GL_NV_vertex_program_functions[] = {
     { VertexAttribs3dvNV_names, VertexAttribs3dvNV_remap_index, -1 },
     { VertexAttribs4fvNV_names, VertexAttribs4fvNV_remap_index, -1 },
     { VertexAttrib2sNV_names, VertexAttrib2sNV_remap_index, -1 },
-    { VertexAttribs3fvNV_names, VertexAttribs3fvNV_remap_index, -1 },
     { ProgramEnvParameter4fvARB_names, ProgramEnvParameter4fvARB_remap_index, -1 },
     { LoadProgramNV_names, LoadProgramNV_remap_index, -1 },
     { VertexAttrib4fvNV_names, VertexAttrib4fvNV_remap_index, -1 },
diff --git a/src/mesa/drivers/dri/ffb/ffb_tex.c b/src/mesa/drivers/dri/ffb/ffb_tex.c
index 69d30aedba..95058e9069 100644
--- a/src/mesa/drivers/dri/ffb/ffb_tex.c
+++ b/src/mesa/drivers/dri/ffb/ffb_tex.c
@@ -30,24 +30,6 @@
 #include "ffb_tex.h"
 
 /* No texture unit, all software. */
-/* XXX this function isn't needed since _mesa_init_driver_functions()
- * will make all these assignments.
- */
 void ffbDDInitTexFuncs(GLcontext *ctx)
 {
-        /*
-	ctx->Driver.ChooseTextureFormat = _mesa_choose_tex_format;
-	ctx->Driver.TexImage1D = _mesa_store_teximage1d;
-	ctx->Driver.TexImage2D = _mesa_store_teximage2d;
-	ctx->Driver.TexImage3D = _mesa_store_teximage3d;
-	ctx->Driver.TexSubImage1D = _mesa_store_texsubimage1d;
-	ctx->Driver.TexSubImage2D = _mesa_store_texsubimage2d;
-	ctx->Driver.TexSubImage3D = _mesa_store_texsubimage3d;
-	ctx->Driver.CopyTexImage1D = _swrast_copy_teximage1d;
-	ctx->Driver.CopyTexImage2D = _swrast_copy_teximage2d;
-	ctx->Driver.CopyTexSubImage1D = _swrast_copy_texsubimage1d;
-	ctx->Driver.CopyTexSubImage2D = _swrast_copy_texsubimage2d;
-	ctx->Driver.CopyTexSubImage3D = _swrast_copy_texsubimage3d;
-	ctx->Driver.TestProxyTexImage = _mesa_test_proxy_teximage;
-	*/
 }
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index c724218cf5..1088a7a607 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -39,12 +39,14 @@
 
 static void prepare_cc_vp( struct brw_context *brw )
 {
+   GLcontext *ctx = &brw->intel.ctx;
    struct brw_cc_viewport ccv;
 
    memset(&ccv, 0, sizeof(ccv));
 
-   ccv.min_depth = 0.0;
-   ccv.max_depth = 1.0;
+   /* _NEW_VIEWPORT */
+   ccv.min_depth = ctx->Viewport.Near;
+   ccv.max_depth = ctx->Viewport.Far;
 
    dri_bo_unreference(brw->cc.vp_bo);
    brw->cc.vp_bo = brw_cache_data( &brw->cache, BRW_CC_VP, &ccv, NULL, 0 );
@@ -52,7 +54,7 @@ static void prepare_cc_vp( struct brw_context *brw )
 
 const struct brw_tracked_state brw_cc_vp = {
    .dirty = {
-      .mesa = 0,
+      .mesa = _NEW_VIEWPORT,
       .brw = BRW_NEW_CONTEXT,
       .cache = 0
    },
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 5762c9577c..234b3744bf 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -43,11 +43,14 @@ struct brw_clip_unit_key {
    unsigned int curbe_offset;
 
    unsigned int nr_urb_entries, urb_size;
+
+   GLboolean depth_clamp;
 };
 
 static void
 clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key)
 {
+   GLcontext *ctx = &brw->intel.ctx;
    memset(key, 0, sizeof(*key));
 
    /* CACHE_NEW_CLIP_PROG */
@@ -62,6 +65,9 @@ clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key)
    /* BRW_NEW_URB_FENCE */
    key->nr_urb_entries = brw->urb.nr_clip_entries;
    key->urb_size = brw->urb.vsize;
+
+   /* _NEW_TRANSOFORM */
+   key->depth_clamp = ctx->Transform.DepthClamp;
 }
 
 static dri_bo *
@@ -117,7 +123,8 @@ clip_unit_create_from_key(struct brw_context *brw,
    clip.clip5.userclip_enable_flags = 0x7f;
    clip.clip5.userclip_must_clip = 1;
    clip.clip5.guard_band_enable = 0;
-   clip.clip5.viewport_z_clip_enable = 1;
+   if (!key->depth_clamp)
+      clip.clip5.viewport_z_clip_enable = 1;
    clip.clip5.viewport_xy_clip_enable = 1;
    clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
    clip.clip5.api_mode = BRW_CLIP_API_OGL;
@@ -168,7 +175,7 @@ static void upload_clip_unit( struct brw_context *brw )
 
 const struct brw_tracked_state brw_clip_unit = {
    .dirty = {
-      .mesa  = 0,
+      .mesa  = _NEW_TRANSFORM,
       .brw   = (BRW_NEW_CURBE_OFFSETS |
 		BRW_NEW_URB_FENCE),
       .cache = CACHE_NEW_CLIP_PROG
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26a64d6528..a5209ac41b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -390,6 +390,8 @@ struct brw_cached_batch_item {
 struct brw_vertex_element {
    const struct gl_client_array *glarray;
 
+   /** The corresponding Mesa vertex attribute */
+   gl_vert_attrib attrib;
    /** Size of a complete element */
    GLuint element_size;
    /** Number of uploaded elements for this input. */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 682094ff13..44bb7bd588 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -25,13 +25,15 @@
  * 
  **************************************************************************/
 
-#include <stdlib.h>
 
 #include "main/glheader.h"
 #include "main/context.h"
 #include "main/state.h"
-#include "main/api_validate.h"
 #include "main/enums.h"
+#include "tnl/tnl.h"
+#include "vbo/vbo_context.h"
+#include "swrast/swrast.h"
+#include "swrast_setup/swrast_setup.h"
 
 #include "brw_draw.h"
 #include "brw_defines.h"
@@ -42,11 +44,6 @@
 #include "intel_batchbuffer.h"
 #include "intel_buffer_objects.h"
 
-#include "tnl/tnl.h"
-#include "vbo/vbo_context.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-
 #define FILE_DEBUG_FLAG DEBUG_BATCH
 
 static GLuint prim_to_hw_prim[GL_POLYGON+1] = {
@@ -145,7 +142,7 @@ static void brw_emit_prim(struct brw_context *brw,
       prim_packet.start_vert_location += brw->ib.start_vertex_offset;
    prim_packet.instance_count = 1;
    prim_packet.start_instance_location = 0;
-   prim_packet.base_vert_location = 0;
+   prim_packet.base_vert_location = prim->basevertex;
 
    /* Can't wrap here, since we rely on the validated state. */
    brw->no_batch_wrap = GL_TRUE;
@@ -187,6 +184,7 @@ static void brw_merge_inputs( struct brw_context *brw,
 
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
       brw->vb.inputs[i].glarray = arrays[i];
+      brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
 
       if (arrays[i]->StrideB != 0)
 	 brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index d49fb0fd95..765ae5a2fe 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -25,9 +25,9 @@
  * 
  **************************************************************************/
 
-#include <stdlib.h>
 
 #include "main/glheader.h"
+#include "main/bufferobj.h"
 #include "main/context.h"
 #include "main/state.h"
 #include "main/api_validate.h"
@@ -384,7 +384,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
 
       input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
 
-      if (input->glarray->BufferObj->Name != 0) {
+      if (_mesa_is_bufferobj(input->glarray->BufferObj)) {
 	 struct intel_buffer_object *intel_buffer =
 	    intel_buffer_object(input->glarray->BufferObj);
 
@@ -423,7 +423,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
 	 /* Queue the buffer object up to be uploaded in the next pass,
 	  * when we've decided if we're doing interleaved or not.
 	  */
-	 if (i == 0) {
+	 if (input->attrib == VERT_ATTRIB_POS) {
 	    /* Position array not properly enabled:
 	     */
             if (input->glarray->StrideB == 0) {
@@ -623,7 +623,7 @@ static void brw_prepare_indices(struct brw_context *brw)
 
    /* Turn into a proper VBO:
     */
-   if (!bufferobj->Name) {
+   if (!_mesa_is_bufferobj(bufferobj)) {
       brw->ib.start_vertex_offset = 0;
 
       /* Get new bufferobj, offset:
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 584fdbdfc3..1638ef8111 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1270,9 +1270,27 @@ post_vs_emit( struct brw_vs_compile *c,
 }
 
 static uint32_t
-get_predicate(uint32_t swizzle)
+get_predicate(const struct prog_instruction *inst)
 {
-   switch (swizzle) {
+   if (inst->DstReg.CondMask == COND_TR)
+      return BRW_PREDICATE_NONE;
+
+   /* All of GLSL only produces predicates for COND_NE and one channel per
+    * vector.  Fail badly if someone starts doing something else, as it might
+    * mean infinite looping or something.
+    *
+    * We'd like to support all the condition codes, but our hardware doesn't
+    * quite match the Mesa IR, which is modeled after the NV extensions.  For
+    * those, the instruction may update the condition codes or not, then any
+    * later instruction may use one of those condition codes.  For gen4, the
+    * instruction may update the flags register based on one of the condition
+    * codes output by the instruction, and then further instructions may
+    * predicate on that.  We can probably support this, but it won't
+    * necessarily be easy.
+    */
+   assert(inst->DstReg.CondMask == COND_NE);
+
+   switch (inst->DstReg.CondSwizzle) {
    case SWIZZLE_XXXX:
       return BRW_PREDICATE_ALIGN16_REPLICATE_X;
    case SWIZZLE_YYYY:
@@ -1282,7 +1300,8 @@ get_predicate(uint32_t swizzle)
    case SWIZZLE_WWWW:
       return BRW_PREDICATE_ALIGN16_REPLICATE_W;
    default:
-      _mesa_problem(NULL, "Unexpected predicate: 0x%08x\n", swizzle);
+      _mesa_problem(NULL, "Unexpected predicate: 0x%08x\n",
+		    inst->DstReg.CondMask);
       return BRW_PREDICATE_NORMAL;
    }
 }
@@ -1294,6 +1313,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
 #define MAX_IF_DEPTH 32
 #define MAX_LOOP_DEPTH 32
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
    const GLuint nr_insns = c->vp->program.Base.NumInstructions;
    GLuint insn, if_depth = 0, loop_depth = 0;
    GLuint end_offset = 0;
@@ -1492,8 +1512,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
       case OPCODE_IF:
 	 assert(if_depth < MAX_IF_DEPTH);
 	 if_inst[if_depth] = brw_IF(p, BRW_EXECUTE_8);
-	 if_inst[if_depth]->header.predicate_control =
-	    get_predicate(inst->DstReg.CondSwizzle);
+	 /* Note that brw_IF smashes the predicate_control field. */
+	 if_inst[if_depth]->header.predicate_control = get_predicate(inst);
 	 if_depth++;
 	 break;
       case OPCODE_ELSE:
@@ -1503,45 +1523,48 @@ void brw_vs_emit(struct brw_vs_compile *c )
          assert(if_depth > 0);
 	 brw_ENDIF(p, if_inst[--if_depth]);
 	 break;			
-#if 0
       case OPCODE_BGNLOOP:
          loop_inst[loop_depth++] = brw_DO(p, BRW_EXECUTE_8);
          break;
       case OPCODE_BRK:
+	 brw_set_predicate_control(p, get_predicate(inst));
          brw_BREAK(p);
-         brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
          break;
       case OPCODE_CONT:
+	 brw_set_predicate_control(p, get_predicate(inst));
          brw_CONT(p);
          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
          break;
       case OPCODE_ENDLOOP: 
          {
             struct brw_instruction *inst0, *inst1;
+	    GLuint br = 1;
+
             loop_depth--;
+
+	    if (BRW_IS_IGDNG(brw))
+	       br = 2;
+
             inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
             /* patch all the BREAK/CONT instructions from last BEGINLOOP */
             while (inst0 > loop_inst[loop_depth]) {
                inst0--;
                if (inst0->header.opcode == BRW_OPCODE_BREAK) {
-                  inst0->bits3.if_else.jump_count = inst1 - inst0 + 1;
+                  inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
                   inst0->bits3.if_else.pop_count = 0;
                }
                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
-                  inst0->bits3.if_else.jump_count = inst1 - inst0;
+                  inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
                   inst0->bits3.if_else.pop_count = 0;
                }
             }
          }
          break;
-#else
-         (void) loop_inst;
-         (void) loop_depth;
-#endif
       case OPCODE_BRA:
-         brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
+	 brw_set_predicate_control(p, get_predicate(inst));
          brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
-         brw_set_predicate_control_flag_value(p, 0xff);
+	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
          break;
       case OPCODE_CAL:
 	 brw_set_access_mode(p, BRW_ALIGN_1);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index ae98b5492d..872b1f3ecf 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -38,6 +38,8 @@
 #include "brw_context.h"
 #include "brw_eu.h"
 
+#define SATURATE (1<<5)
+
 /* A big lookup table is used to figure out which and how many
  * additional regs will inserted before the main payload in the WM
  * program execution.  These mainly relate to depth and stencil
@@ -203,7 +205,6 @@ struct brw_wm_compile {
    GLuint fp_temp;
    GLuint fp_interp_emitted;
    GLuint fp_fragcolor_emitted;
-   GLuint fp_deriv_emitted;
 
    struct prog_src_register pixel_xy;
    struct prog_src_register delta_xy;
@@ -299,5 +300,10 @@ void brw_wm_lookup_iz( GLuint line_aa,
 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
 
+void emit_ddxy(struct brw_compile *p,
+	       const struct brw_reg *dst,
+	       GLuint mask,
+	       GLboolean is_ddx,
+	       const struct brw_reg *arg0);
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 981864323e..bf80a2942a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -34,8 +34,6 @@
 #include "brw_context.h"
 #include "brw_wm.h"
 
-#define SATURATE (1<<5)
-
 /* Not quite sure how correct this is - need to understand horiz
  * vs. vertical strides a little better.
  */
@@ -281,6 +279,79 @@ static void emit_frontfacing( struct brw_compile *p,
    brw_set_predicate_control_flag_value(p, 0xff);
 }
 
+/* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
+ * looking like:
+ *
+ * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
+ *
+ * and we're trying to produce:
+ *
+ *           DDX                     DDY
+ * dst: (ss0.tr - ss0.tl)     (ss0.tl - ss0.bl)
+ *      (ss0.tr - ss0.tl)     (ss0.tr - ss0.br)
+ *      (ss0.br - ss0.bl)     (ss0.tl - ss0.bl)
+ *      (ss0.br - ss0.bl)     (ss0.tr - ss0.br)
+ *      (ss1.tr - ss1.tl)     (ss1.tl - ss1.bl)
+ *      (ss1.tr - ss1.tl)     (ss1.tr - ss1.br)
+ *      (ss1.br - ss1.bl)     (ss1.tl - ss1.bl)
+ *      (ss1.br - ss1.bl)     (ss1.tr - ss1.br)
+ *
+ * and add another set of two more subspans if in 16-pixel dispatch mode.
+ *
+ * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
+ * for each pair, and vertstride = 2 jumps us 2 elements after processing a
+ * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
+ * between each other.  We could probably do it like ddx and swizzle the right
+ * order later, but bail for now and just produce
+ * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
+ */
+void emit_ddxy(struct brw_compile *p,
+	       const struct brw_reg *dst,
+	       GLuint mask,
+	       GLboolean is_ddx,
+	       const struct brw_reg *arg0)
+{
+   int i;
+   struct brw_reg src0, src1;
+
+   if (mask & SATURATE)
+      brw_set_saturate(p, 1);
+   for (i = 0; i < 4; i++ ) {
+      if (mask & (1<<i)) {
+	 if (is_ddx) {
+	    src0 = brw_reg(arg0[i].file, arg0[i].nr, 1,
+			   BRW_REGISTER_TYPE_F,
+			   BRW_VERTICAL_STRIDE_2,
+			   BRW_WIDTH_2,
+			   BRW_HORIZONTAL_STRIDE_0,
+			   BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
+	    src1 = brw_reg(arg0[i].file, arg0[i].nr, 0,
+			   BRW_REGISTER_TYPE_F,
+			   BRW_VERTICAL_STRIDE_2,
+			   BRW_WIDTH_2,
+			   BRW_HORIZONTAL_STRIDE_0,
+			   BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
+	 } else {
+	    src0 = brw_reg(arg0[i].file, arg0[i].nr, 0,
+			   BRW_REGISTER_TYPE_F,
+			   BRW_VERTICAL_STRIDE_4,
+			   BRW_WIDTH_4,
+			   BRW_HORIZONTAL_STRIDE_0,
+			   BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
+	    src1 = brw_reg(arg0[i].file, arg0[i].nr, 2,
+			   BRW_REGISTER_TYPE_F,
+			   BRW_VERTICAL_STRIDE_4,
+			   BRW_WIDTH_4,
+			   BRW_HORIZONTAL_STRIDE_0,
+			   BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
+	 }
+	 brw_ADD(p, dst[i], src0, negate(src1));
+      }
+   }
+   if (mask & SATURATE)
+      brw_set_saturate(p, 0);
+}
+
 static void emit_alu1( struct brw_compile *p, 
 		       struct brw_instruction *(*func)(struct brw_compile *, 
 						       struct brw_reg, 
@@ -1272,6 +1343,14 @@ void brw_wm_emit( struct brw_wm_compile *c )
 	 emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]);
 	 break;
 
+      case OPCODE_DDX:
+	 emit_ddxy(p, dst, dst_flags, GL_TRUE, args[0]);
+	 break;
+
+      case OPCODE_DDY:
+	 emit_ddxy(p, dst, dst_flags, GL_FALSE, args[0]);
+	 break;
+
       case OPCODE_DP3:
 	 emit_dp3(p, dst, dst_flags, args[0], args[1]);
 	 break;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c
index 123fe841c3..4e3edfbbff 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_fp.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c
@@ -494,38 +494,6 @@ static void emit_interp( struct brw_wm_compile *c,
    c->fp_interp_emitted |= 1<<idx;
 }
 
-static void emit_ddx( struct brw_wm_compile *c,
-        const struct prog_instruction *inst )
-{
-    GLuint idx = inst->SrcReg[0].Index;
-    struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx);
-
-    c->fp_deriv_emitted |= 1<<idx;
-    emit_op(c,
-            OPCODE_DDX,
-            inst->DstReg,
-            0,
-            interp,
-            get_pixel_w(c),
-            src_undef());
-}
-
-static void emit_ddy( struct brw_wm_compile *c,
-        const struct prog_instruction *inst )
-{
-    GLuint idx = inst->SrcReg[0].Index;
-    struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx);
-
-    c->fp_deriv_emitted |= 1<<idx;
-    emit_op(c,
-            OPCODE_DDY,
-            inst->DstReg,
-            0,
-            interp,
-            get_pixel_w(c),
-            src_undef());
-}
-
 /***********************************************************************
  * Hacks to extend the program parameter and constant lists.
  */
@@ -1186,12 +1154,6 @@ void brw_wm_pass_fp( struct brw_wm_compile *c )
 	  */
 	 out->DstReg.WriteMask = 0;
 	 break;
-      case OPCODE_DDX:
-	 emit_ddx(c, inst);
-	 break;
-      case OPCODE_DDY:
-         emit_ddy(c, inst);
-	break;
       case OPCODE_END:
 	 emit_fb_write(c);
 	 break;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 7c210abbce..c9fe1dd8ad 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -22,6 +22,7 @@ static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
 {
     int i;
+
     for (i = 0; i < fp->Base.NumInstructions; i++) {
 	const struct prog_instruction *inst = &fp->Base.Instructions[i];
 	switch (inst->Opcode) {
@@ -31,8 +32,6 @@ GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
 	    case OPCODE_CAL:
 	    case OPCODE_BRK:
 	    case OPCODE_RET:
-	    case OPCODE_DDX:
-	    case OPCODE_DDY:
 	    case OPCODE_NOISE1:
 	    case OPCODE_NOISE2:
 	    case OPCODE_NOISE3:
@@ -293,7 +292,7 @@ static void prealloc_reg(struct brw_wm_compile *c)
     int i, j;
     struct brw_reg reg;
     int urb_read_length = 0;
-    GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
+    GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted;
     GLuint reg_index = 0;
 
     memset(c->used_grf, GL_FALSE, sizeof(c->used_grf));
@@ -1474,61 +1473,6 @@ static void emit_sne(struct brw_wm_compile *c,
     emit_sop(c, inst, BRW_CONDITIONAL_NEQ);
 }
 
-static void emit_ddx(struct brw_wm_compile *c,
-                     const struct prog_instruction *inst)
-{
-    struct brw_compile *p = &c->func;
-    GLuint mask = inst->DstReg.WriteMask;
-    struct brw_reg interp[4];
-    struct brw_reg dst;
-    struct brw_reg src0, w;
-    GLuint nr, i;
-    src0 = get_src_reg(c, inst, 0, 0);
-    w = get_src_reg(c, inst, 1, 3);
-    nr = src0.nr;
-    interp[0] = brw_vec1_grf(nr, 0);
-    interp[1] = brw_vec1_grf(nr, 4);
-    interp[2] = brw_vec1_grf(nr+1, 0);
-    interp[3] = brw_vec1_grf(nr+1, 4);
-    brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
-    for(i = 0; i < 4; i++ ) {
-        if (mask & (1<<i)) {
-            dst = get_dst_reg(c, inst, i);
-            brw_MOV(p, dst, interp[i]);
-            brw_MUL(p, dst, dst, w);
-        }
-    }
-    brw_set_saturate(p, 0);
-}
-
-static void emit_ddy(struct brw_wm_compile *c,
-                     const struct prog_instruction *inst)
-{
-    struct brw_compile *p = &c->func;
-    GLuint mask = inst->DstReg.WriteMask;
-    struct brw_reg interp[4];
-    struct brw_reg dst;
-    struct brw_reg src0, w;
-    GLuint nr, i;
-
-    src0 = get_src_reg(c, inst, 0, 0);
-    nr = src0.nr;
-    w = get_src_reg(c, inst, 1, 3);
-    interp[0] = brw_vec1_grf(nr, 0);
-    interp[1] = brw_vec1_grf(nr, 4);
-    interp[2] = brw_vec1_grf(nr+1, 0);
-    interp[3] = brw_vec1_grf(nr+1, 4);
-    brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
-    for(i = 0; i < 4; i++ ) {
-        if (mask & (1<<i)) {
-            dst = get_dst_reg(c, inst, i);
-            brw_MOV(p, dst, suboffset(interp[i], 1));
-            brw_MUL(p, dst, dst, w);
-        }
-    }
-    brw_set_saturate(p, 0);
-}
-
 static INLINE struct brw_reg high_words( struct brw_reg reg )
 {
     return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_W ), 1 ),
@@ -2780,6 +2724,21 @@ static void post_wm_emit( struct brw_wm_compile *c )
     brw_resolve_cals(&c->func);
 }
 
+static void
+get_argument_regs(struct brw_wm_compile *c,
+		  const struct prog_instruction *inst,
+		  int index,
+		  struct brw_reg *regs,
+		  int mask)
+{
+    int i;
+
+    for (i = 0; i < 4; i++) {
+	if (mask & (1 << i))
+	    regs[i] = get_src_reg(c, inst, index, i);
+    }
+}
+
 static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 {
 #define MAX_IF_DEPTH 32
@@ -2797,6 +2756,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 
     for (i = 0; i < c->nr_fp_insns; i++) {
         const struct prog_instruction *inst = &c->prog_instructions[i];
+	int dst_flags;
+	struct brw_reg args[3][4], dst[4];
+	int j;
 
         c->cur_inst = i;
 
@@ -2814,6 +2776,10 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 	else
 	    brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
 
+	dst_flags = inst->DstReg.WriteMask;
+	if (inst->SaturateMode == SATURATE_ZERO_ONE)
+	    dst_flags |= SATURATE;
+
 	switch (inst->Opcode) {
 	    case WM_PIXELXY:
 		emit_pixel_xy(c, inst);
@@ -2899,10 +2865,16 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 		emit_min_max(c, inst);
 		break;
 	    case OPCODE_DDX:
-		emit_ddx(c, inst);
-		break;
 	    case OPCODE_DDY:
-                emit_ddy(c, inst);
+		for (j = 0; j < 4; j++) {
+		    if (inst->DstReg.WriteMask & (1 << j))
+			dst[j] = get_dst_reg(c, inst, j);
+		    else
+			dst[j] = brw_null_reg();
+		}
+		get_argument_regs(c, inst, 0, args[0], WRITEMASK_XYZW);
+		emit_ddxy(p, dst, dst_flags, (inst->Opcode == OPCODE_DDX),
+			  args[0]);
                 break;
 	    case OPCODE_SLT:
 		emit_slt(c, inst);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass1.c b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
index 9c68bfd78b..b449394029 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass1.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
@@ -178,6 +178,11 @@ void brw_wm_pass1( struct brw_wm_compile *c )
 	 read1 = writemask;
 	 break;
 
+      case OPCODE_DDX:
+      case OPCODE_DDY:
+	 read0 = writemask;
+	 break;
+
       case OPCODE_MAD:	
       case OPCODE_CMP:
       case OPCODE_LRP:
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 39f8c6d522..361f91292b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -107,6 +107,12 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
    /* as far as we can tell */
    key->computes_depth =
       (fp->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) != 0;
+   /* BRW_NEW_DEPTH_BUFFER
+    * Override for NULL depthbuffer case, required by the Pixel Shader Computed
+    * Depth field.
+    */
+   if (brw->state.depth_region == NULL)
+      key->computes_depth = 0;
 
    /* _NEW_COLOR */
    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
@@ -300,6 +306,7 @@ const struct brw_tracked_state brw_wm_unit = {
 
       .brw = (BRW_NEW_FRAGMENT_PROGRAM | 
 	      BRW_NEW_CURBE_OFFSETS |
+	      BRW_NEW_DEPTH_BUFFER |
 	      BRW_NEW_NR_WM_SURFACES),
 
       .cache = (CACHE_NEW_WM_PROG |
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 096f74394e..51539ac1e7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -545,15 +545,20 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 		       irb->texformat->MesaFormat);
       }
       key.tiling = region->tiling;
-      key.width = region->width;
-      key.height = region->height;
+      if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) {
+	 key.width = rb->Width;
+	 key.height = rb->Height;
+      } else {
+	 key.width = region->width;
+	 key.height = region->height;
+      }
       key.pitch = region->pitch;
       key.cpp = region->cpp;
       key.draw_offset = region->draw_offset; /* cur 3d or cube face offset */
    } else {
       key.surface_type = BRW_SURFACE_NULL;
       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-      key.tiling = 0;
+      key.tiling = I915_TILING_X;
       key.width = 1;
       key.height = 1;
       key.cpp = 4;
@@ -629,7 +634,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 	 drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 				 offsetof(struct brw_surface_state, ss1),
 				 region_bo,
-				 surf.ss1.base_addr,
+				 surf.ss1.base_addr - region_bo->offset,
 				 I915_GEM_DOMAIN_RENDER,
 				 I915_GEM_DOMAIN_RENDER);
       }
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 0c5be4c798..43141c509c 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -26,9 +26,6 @@
  **************************************************************************/
 
 
-#include <stdio.h>
-#include <errno.h>
-
 #include "main/mtypes.h"
 #include "main/context.h"
 #include "main/enums.h"
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index 3c38f1676c..3dc8653a73 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -66,6 +66,7 @@
 #define PCI_CHIP_Q45_G                  0x2E12
 #define PCI_CHIP_G45_G                  0x2E22
 #define PCI_CHIP_G41_G                  0x2E32
+#define PCI_CHIP_B43_G                  0x2E42
 
 #define PCI_CHIP_ILD_G                  0x0042
 #define PCI_CHIP_ILM_G                  0x0046
@@ -83,7 +84,8 @@
 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
                                  devid == PCI_CHIP_Q45_G || \
                                  devid == PCI_CHIP_G45_G || \
-                                 devid == PCI_CHIP_G41_G)
+                                 devid == PCI_CHIP_G41_G || \
+                                 devid == PCI_CHIP_B43_G)
 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 #define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
 
diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index bce23724b3..fef977f465 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -38,6 +38,7 @@
 #include "intel_fbo.h"
 #include "intel_pixel.h"
 #include "intel_regions.h"
+#include "intel_batchbuffer.h"
 
 #define FILE_DEBUG_FLAG DEBUG_BLIT
 
@@ -170,7 +171,9 @@ intelClear(GLcontext *ctx, GLbitfield mask)
 	 }
 	 DBG("\n");
       }
-      _mesa_meta_clear(&intel->ctx, tri_mask);
+
+      _mesa_meta_Clear(&intel->ctx, tri_mask);
+      intel_batchbuffer_flush(intel->batch);
    }
 
    if (swrast_mask) {
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 89f99f7ffd..d49d95768d 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -162,6 +162,9 @@ intelGetString(GLcontext * ctx, GLenum name)
       case PCI_CHIP_G41_G:
          chipset = "Intel(R) G41";
          break;
+      case PCI_CHIP_B43_G:
+         chipset = "Intel(R) B43";
+         break;
       case PCI_CHIP_ILD_G:
          chipset = "Intel(R) IGDNG_D";
          break;
@@ -504,7 +507,8 @@ intel_flush(GLcontext *ctx, GLboolean needs_mi_flush)
 
       if (screen->dri2.loader &&
           (screen->dri2.loader->base.version >= 2)
-	  && (screen->dri2.loader->flushFrontBuffer != NULL)) {
+	  && (screen->dri2.loader->flushFrontBuffer != NULL) &&
+          intel->driDrawable && intel->driDrawable->loaderPrivate) {
 	 (*screen->dri2.loader->flushFrontBuffer)(intel->driDrawable,
 						  intel->driDrawable->loaderPrivate);
 
@@ -584,11 +588,6 @@ intelInitDriverFunctions(struct dd_function_table *functions)
    functions->GetString = intelGetString;
    functions->UpdateState = intelInvalidateState;
 
-   functions->CopyColorTable = _swrast_CopyColorTable;
-   functions->CopyColorSubTable = _swrast_CopyColorSubTable;
-   functions->CopyConvolutionFilter1D = _swrast_CopyConvolutionFilter1D;
-   functions->CopyConvolutionFilter2D = _swrast_CopyConvolutionFilter2D;
-
    intelInitTextureFuncs(functions);
    intelInitTextureImageFuncs(functions);
    intelInitTextureSubImageFuncs(functions);
@@ -641,10 +640,6 @@ intelInitContext(struct intel_context *intel,
       intel->maxBatchSize = BATCH_SZ;
 
    intel->bufmgr = intelScreen->bufmgr;
-
-   if (0) /* for debug */
-      drm_intel_bufmgr_set_debug(intel->bufmgr, 1);
-
    intel->ttm = intelScreen->ttm;
    if (intel->ttm) {
       int bo_reuse_mode;
@@ -923,6 +918,14 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
 GLboolean
 intelUnbindContext(__DRIcontextPrivate * driContextPriv)
 {
+   struct intel_context *intel =
+      (struct intel_context *) driContextPriv->driverPrivate;
+
+   /* Deassociate the context with the drawables.
+    */
+   intel->driDrawable = NULL;
+   intel->driReadDrawable = NULL;
+
    return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c
index 2e61c556d8..5431cf90a1 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -31,6 +31,7 @@
 
 
 #define need_GL_ARB_copy_buffer
+#define need_GL_ARB_draw_elements_base_vertex
 #define need_GL_ARB_framebuffer_object
 #define need_GL_ARB_map_buffer_range
 #define need_GL_ARB_occlusion_query
@@ -73,6 +74,7 @@
  */
 static const struct dri_extension card_extensions[] = {
    { "GL_ARB_copy_buffer",                GL_ARB_copy_buffer_functions },
+   { "GL_ARB_draw_elements_base_vertex",  GL_ARB_draw_elements_base_vertex_functions },
    { "GL_ARB_half_float_pixel",           NULL },
    { "GL_ARB_map_buffer_range",           GL_ARB_map_buffer_range_functions },
    { "GL_ARB_multitexture",               NULL },
@@ -139,6 +141,7 @@ static const struct dri_extension i915_extensions[] = {
 
 /** i965-only extensions */
 static const struct dri_extension brw_extensions[] = {
+   { "GL_ARB_depth_clamp",                NULL },
    { "GL_ARB_depth_texture",              NULL },
    { "GL_ARB_fragment_program",           NULL },
    { "GL_ARB_fragment_program_shadow",    NULL },
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 804c034840..8dfb24290d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -715,5 +715,5 @@ intel_fbo_init(struct intel_context *intel)
    intel->ctx.Driver.FinishRenderTexture = intel_finish_render_texture;
    intel->ctx.Driver.ResizeBuffers = intel_resize_buffers;
    intel->ctx.Driver.ValidateFramebuffer = intel_validate_framebuffer;
-   intel->ctx.Driver.BlitFramebuffer = _mesa_meta_blit_framebuffer;
+   intel->ctx.Driver.BlitFramebuffer = _mesa_meta_BlitFramebuffer;
 }
diff --git a/src/mesa/drivers/dri/intel/intel_generatemipmap.c b/src/mesa/drivers/dri/intel/intel_generatemipmap.c
index fe986092db..237754d469 100644
--- a/src/mesa/drivers/dri/intel/intel_generatemipmap.c
+++ b/src/mesa/drivers/dri/intel/intel_generatemipmap.c
@@ -223,10 +223,6 @@ fail:
  *
  * The texture object's miptree must be mapped.
  *
- * It would be really nice if this was just called by Mesa whenever mipmaps
- * needed to be regenerated, rather than us having to remember to do so in
- * each texture image modification path.
- *
  * This function should also include an accelerated path.
  */
 void
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index b543a0bbc3..9a0bcc07a5 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -209,7 +209,7 @@ do_blit_bitmap( GLcontext *ctx,
    if (!dst)
        return GL_FALSE;
 
-   if (unpack->BufferObj->Name) {
+   if (_mesa_is_bufferobj(unpack->BufferObj)) {
       bitmap = map_pbo(ctx, width, height, unpack, bitmap);
       if (bitmap == NULL)
 	 return GL_TRUE;	/* even though this is an error, we're done */
@@ -329,7 +329,7 @@ out:
    if (INTEL_DEBUG & DEBUG_SYNC)
       intel_batchbuffer_flush(intel->batch);
 
-   if (unpack->BufferObj->Name) {
+   if (_mesa_is_bufferobj(unpack->BufferObj)) {
       /* done with PBO so unmap it now */
       ctx->Driver.UnmapBuffer(ctx, GL_PIXEL_UNPACK_BUFFER_EXT,
                               unpack->BufferObj);
@@ -418,7 +418,7 @@ intel_texture_bitmap(GLcontext * ctx,
       return GL_FALSE;
    }
 
-   if (unpack->BufferObj->Name) {
+   if (_mesa_is_bufferobj(unpack->BufferObj)) {
       bitmap = map_pbo(ctx, width, height, unpack, bitmap);
       if (bitmap == NULL)
 	 return GL_TRUE;	/* even though this is an error, we're done */
@@ -428,7 +428,7 @@ intel_texture_bitmap(GLcontext * ctx,
    a8_bitmap = _mesa_calloc(width * height);
    _mesa_expand_bitmap(width, height, unpack, bitmap, a8_bitmap, width, 0xff);
 
-   if (unpack->BufferObj->Name) {
+   if (_mesa_is_bufferobj(unpack->BufferObj)) {
       /* done with PBO so unmap it now */
       ctx->Driver.UnmapBuffer(ctx, GL_PIXEL_UNPACK_BUFFER_EXT,
                               unpack->BufferObj);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
index 07ca8f7ddb..f058b3c8e4 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
@@ -240,5 +240,5 @@ intelCopyPixels(GLcontext * ctx,
       return;
 
    /* this will use swrast if needed */
-   _mesa_meta_copy_pixels(ctx, srcx, srcy, width, height, destx, desty, type);
+   _mesa_meta_CopyPixels(ctx, srcx, srcy, width, height, destx, desty, type);
 }
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 8c113881d6..5ffa847fd4 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -42,6 +42,7 @@
 #include "main/depth.h"
 #include "main/hash.h"
 #include "main/blend.h"
+#include "swrast/swrast.h"
 #include "drivers/common/meta.h"
 
 #include "intel_context.h"
@@ -53,7 +54,7 @@
 #include "intel_fbo.h"
 
 
-/** XXX compare perf of this vs. _mesa_meta_draw_pixels(STENCIL) */
+/** XXX compare perf of this vs. _mesa_meta_DrawPixels(STENCIL) */
 static GLboolean
 intel_stencil_drawpixels(GLcontext * ctx,
 			 GLint x, GLint y,
@@ -260,10 +261,25 @@ intelDrawPixels(GLcontext * ctx,
                 const struct gl_pixelstore_attrib *unpack,
                 const GLvoid * pixels)
 {
+#if 0
+   /* XXX this function doesn't seem to work reliably even when all
+    * the pre-requisite conditions are met.
+    * Note that this function is never hit with conform.
+    * Fall back to swrast because even the _mesa_meta_DrawPixels() approach
+    * isn't working because of an apparent stencil bug.
+    */
    if (intel_stencil_drawpixels(ctx, x, y, width, height, format, type,
 				unpack, pixels))
       return;
+#else
+   (void) intel_stencil_drawpixels; /* silence warning */
+   if (format == GL_STENCIL_INDEX) {
+      _swrast_DrawPixels(ctx, x, y, width, height, format, type,
+                         unpack, pixels);
+      return;
+   }
+#endif
 
-   _mesa_meta_draw_pixels(ctx, x, y, width, height, format, type,
-                          unpack, pixels);
+   _mesa_meta_DrawPixels(ctx, x, y, width, height, format, type,
+                         unpack, pixels);
 }
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index 8713463ace..bc67f6242a 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -180,16 +180,7 @@ do_blit_readpixels(GLcontext * ctx,
    if (!src)
       return GL_FALSE;
 
-   if (pack->BufferObj->Name) {
-      /* XXX This validation should be done by core mesa:
-       */
-      if (!_mesa_validate_pbo_access(2, pack, width, height, 1,
-                                     format, type, pixels)) {
-         _mesa_error(ctx, GL_INVALID_OPERATION, "glDrawPixels");
-         return GL_TRUE;
-      }
-   }
-   else {
+   if (!_mesa_is_bufferobj(pack->BufferObj)) {
       /* PBO only for now:
        */
       if (INTEL_DEBUG & DEBUG_PIXEL)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 068a3f3379..a86c66a844 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -196,6 +196,13 @@ intel_region_alloc(struct intel_context *intel,
    else
       height = ALIGN(height, 2);
 
+   /* If we're untiled, we have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
+   height = ALIGN(height, 2);
+
    if (expect_accelerated_upload) {
       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
 					     pitch * cpp * height, 64);
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 8df4990880..28eabbc005 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -444,23 +444,30 @@ intel_renderbuffer_unmap(struct intel_context *intel,
  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
  */
 static void
-intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
+intel_map_unmap_framebuffer(struct intel_context *intel,
+			    struct gl_framebuffer *fb,
+			    GLboolean map)
 {
-   GLcontext *ctx = &intel->ctx;
-   GLuint i, j;
+   GLuint i;
 
    /* color draw buffers */
-   for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
+   for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
       if (map)
-	 intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
+         intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
       else
-	 intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
+         intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
    }
 
+   /* color read buffer */
+   if (map)
+      intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
+   else
+      intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
+
    /* check for render to textures */
    for (i = 0; i < BUFFER_COUNT; i++) {
       struct gl_renderbuffer_attachment *att =
-         ctx->DrawBuffer->Attachment + i;
+         fb->Attachment + i;
       struct gl_texture_object *tex = att->Texture;
       if (tex) {
          /* render to texture */
@@ -472,34 +479,23 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
       }
    }
 
-   /* color read buffers */
-   if (map)
-      intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
-   else
-      intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
-
    /* depth buffer (Note wrapper!) */
-   if (ctx->DrawBuffer->_DepthBuffer) {
+   if (fb->_DepthBuffer) {
       if (map)
-	 intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
+         intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
       else
-	 intel_renderbuffer_unmap(intel,
-				  ctx->DrawBuffer->_DepthBuffer->Wrapped);
+         intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
    }
 
    /* stencil buffer (Note wrapper!) */
-   if (ctx->DrawBuffer->_StencilBuffer) {
+   if (fb->_StencilBuffer) {
       if (map)
-	 intel_renderbuffer_map(intel,
-				ctx->DrawBuffer->_StencilBuffer->Wrapped);
+         intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
       else
-	 intel_renderbuffer_unmap(intel,
-				  ctx->DrawBuffer->_StencilBuffer->Wrapped);
+         intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
    }
 }
 
-
-
 /**
  * Prepare for software rendering.  Map current read/draw framebuffers'
  * renderbuffes and all currently bound texture objects.
@@ -522,7 +518,9 @@ intelSpanRenderStart(GLcontext * ctx)
       }
    }
 
-   intel_map_unmap_buffers(intel, GL_TRUE);
+   intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
+   if (ctx->ReadBuffer != ctx->DrawBuffer)
+      intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 }
 
 /**
@@ -544,7 +542,9 @@ intelSpanRenderFinish(GLcontext * ctx)
       }
    }
 
-   intel_map_unmap_buffers(intel, GL_FALSE);
+   intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
+   if (ctx->ReadBuffer != ctx->DrawBuffer)
+      intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 
    UNLOCK_HARDWARE(intel);
 }
@@ -711,6 +711,9 @@ intel_set_span_functions(struct intel_context *intel,
 	    intel_YTile_InitStencilPointers_z24_s8(rb);
 	    break;
 	 }
+      } else {
+	 _mesa_problem(NULL,
+		       "Unexpected ActualFormat in intelSetSpanFunctions");
       }
       break;
    default:
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 028b49c14d..ac557a9200 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -30,7 +30,8 @@
 #include "main/image.h"
 #include "main/teximage.h"
 #include "main/mipmap.h"
-#include "swrast/swrast.h"
+
+#include "drivers/common/meta.h"
 
 #include "intel_screen.h"
 #include "intel_context.h"
@@ -90,7 +91,6 @@ do_copy_texsubimage(struct intel_context *intel,
                     GLint x, GLint y, GLsizei width, GLsizei height)
 {
    GLcontext *ctx = &intel->ctx;
-   struct gl_texture_object *texObj = intelImage->base.TexObject;
    const struct intel_region *src =
       get_teximage_source(intel, internalFormat);
 
@@ -170,11 +170,6 @@ do_copy_texsubimage(struct intel_context *intel,
 
    UNLOCK_HARDWARE(intel);
 
-   /* GL_SGIS_generate_mipmap */
-   if (intelImage->level == texObj->BaseLevel && texObj->GenerateMipmap) {
-      intel_generate_mipmap(ctx, target, texObj);
-   }
-
    return GL_TRUE;
 }
 
@@ -221,8 +216,8 @@ intelCopyTexImage1D(GLcontext * ctx, GLenum target, GLint level,
    return;
 
  fail:
-   _swrast_copy_teximage1d(ctx, target, level, internalFormat, x, y,
-                           width, border);
+   _mesa_meta_CopyTexImage1D(ctx, target, level, internalFormat, x, y,
+                             width, border);
 }
 
 
@@ -269,8 +264,8 @@ intelCopyTexImage2D(GLcontext * ctx, GLenum target, GLint level,
    return;
 
  fail:
-   _swrast_copy_teximage2d(ctx, target, level, internalFormat, x, y,
-                           width, height, border);
+   _mesa_meta_CopyTexImage2D(ctx, target, level, internalFormat, x, y,
+                             width, height, border);
 }
 
 
@@ -294,7 +289,7 @@ intelCopyTexSubImage1D(GLcontext * ctx, GLenum target, GLint level,
    if (!do_copy_texsubimage(intel_context(ctx), target,
                             intel_texture_image(texImage),
                             internalFormat, xoffset, 0, x, y, width, 1)) {
-      _swrast_copy_texsubimage1d(ctx, target, level, xoffset, x, y, width);
+      _mesa_meta_CopyTexSubImage1D(ctx, target, level, xoffset, x, y, width);
    }
 }
 
@@ -320,10 +315,10 @@ intelCopyTexSubImage2D(GLcontext * ctx, GLenum target, GLint level,
                             internalFormat,
                             xoffset, yoffset, x, y, width, height)) {
 
-      DBG("%s - fallback to swrast\n", __FUNCTION__);
+      DBG("%s - fallback to _mesa_meta_CopyTexSubImage2D\n", __FUNCTION__);
 
-      _swrast_copy_texsubimage2d(ctx, target, level,
-                                 xoffset, yoffset, x, y, width, height);
+      _mesa_meta_CopyTexSubImage2D(ctx, target, level,
+                                   xoffset, yoffset, x, y, width, height);
    }
 }
 
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index c5f5220837..66201b1f46 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -1,15 +1,11 @@
 
-#include <stdlib.h>
-#include <stdio.h>
-
 #include "main/glheader.h"
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/enums.h"
-#include "main/colortab.h"
+#include "main/bufferobj.h"
 #include "main/convolve.h"
 #include "main/context.h"
-#include "main/simple_list.h"
 #include "main/texcompress.h"
 #include "main/texformat.h"
 #include "main/texgetimage.h"
@@ -206,7 +202,7 @@ try_pbo_upload(struct intel_context *intel,
    GLuint src_offset, src_stride;
    GLuint dst_offset, dst_stride;
 
-   if (unpack->BufferObj->Name == 0 ||
+   if (!_mesa_is_bufferobj(unpack->BufferObj) ||
        intel->ctx._ImageTransferState ||
        unpack->SkipPixels || unpack->SkipRows) {
       DBG("%s: failure 1\n", __FUNCTION__);
@@ -264,7 +260,7 @@ try_pbo_zcopy(struct intel_context *intel,
    GLuint src_offset, src_stride;
    GLuint dst_offset, dst_stride;
 
-   if (unpack->BufferObj->Name == 0 ||
+   if (!_mesa_is_bufferobj(unpack->BufferObj) ||
        intel->ctx._ImageTransferState ||
        unpack->SkipPixels || unpack->SkipRows) {
       DBG("%s: failure 1\n", __FUNCTION__);
@@ -427,7 +423,7 @@ intelTexImage(GLcontext * ctx,
     */
    if (dims <= 2 &&
        intelImage->mt &&
-       unpack->BufferObj->Name != 0 &&
+       _mesa_is_bufferobj(unpack->BufferObj) &&
        check_pbo_format(internalFormat, format,
                         type, intelImage->base.TexFormat)) {
 
@@ -550,11 +546,6 @@ intelTexImage(GLcontext * ctx,
    }
 
    UNLOCK_HARDWARE(intel);
-
-   /* GL_SGIS_generate_mipmap */
-   if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-      intel_generate_mipmap(ctx, target, texObj);
-   }
 }
 
 
diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
index 89037073f8..751ec2c98c 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
@@ -129,11 +129,6 @@ intelTexSubimage(GLcontext * ctx,
    }
 
    UNLOCK_HARDWARE(intel);
-
-   /* GL_SGIS_generate_mipmap */
-   if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-      intel_generate_mipmap(ctx, target, texObj);
-   }
 }
 
 
diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
index 42635bf9d9..fbce70c37b 100644
--- a/src/mesa/drivers/dri/r200/Makefile
+++ b/src/mesa/drivers/dri/r200/Makefile
@@ -55,8 +55,7 @@ C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
 
 X86_SOURCES = 
 
-DRIVER_DEFINES = -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R200 \
-				 -Wall
+DRIVER_DEFINES = -DRADEON_R200 -Wall
 
 DRI_LIB_DEPS += $(RADEON_LDFLAGS)
 
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile
index 06c31ce7f2..c64f940623 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -63,8 +63,7 @@ DRIVER_SOURCES = \
 
 C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
 
-DRIVER_DEFINES = -DCOMPILE_R300 -DR200_MERGED=0 \
-	-DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300 \
+DRIVER_DEFINES = -DRADEON_R300
 #	-DRADEON_BO_TRACK \
 	-Wall
 
diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
index 58953f6b04..2dad3dba4a 100644
--- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
@@ -352,7 +352,7 @@ void r300BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compi
 	if (emit.current_node < 3) {
 		int shift = 3 - emit.current_node;
 		int i;
-		for(i = 0; i <= emit.current_node; ++i)
+		for(i = emit.current_node; i >= 0; --i)
 			code->code_addr[shift + i] = code->code_addr[i];
 		for(i = 0; i < shift; ++i)
 			code->code_addr[i] = 0;
diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
index c64648ff3b..ac72f8cbb6 100644
--- a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
+++ b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
@@ -81,6 +81,7 @@ static unsigned long t_src_class(rc_register_file file)
 	default:
 		fprintf(stderr, "%s: Bad register file %i\n", __FUNCTION__, file);
 		/* fall-through */
+	case RC_FILE_NONE:
 	case RC_FILE_TEMPORARY:
 		return PVS_SRC_REG_TEMPORARY;
 	case RC_FILE_INPUT:
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
index 041e3cab82..e25bc4ec87 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
@@ -500,23 +500,23 @@ static void sincos_constants(struct radeon_compiler* c, unsigned int *constants)
  * MAD dest, tmp.y, weight, tmp.x
  */
 static void sin_approx(
-	struct radeon_compiler* c, struct rc_instruction * after,
+	struct radeon_compiler* c, struct rc_instruction * before,
 	struct rc_dst_register dst, struct rc_src_register src, const unsigned int* constants)
 {
 	unsigned int tempreg = rc_find_free_temporary(c);
 
-	emit2(c, after->Prev, RC_OPCODE_MUL, 0, dstregtmpmask(tempreg, RC_MASK_XY),
+	emit2(c, before, RC_OPCODE_MUL, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 		swizzle(src, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 		srcreg(RC_FILE_CONSTANT, constants[0]));
-	emit3(c, after->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_X),
+	emit3(c, before, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_X),
 		swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 		absolute(swizzle(src, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 		swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
-	emit3(c, after->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_Y),
+	emit3(c, before, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_Y),
 		swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 		absolute(swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 		negate(swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)));
-	emit3(c, after->Prev, RC_OPCODE_MAD, 0, dst,
+	emit3(c, before, RC_OPCODE_MAD, 0, dst,
 		swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 		swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 		swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
@@ -556,7 +556,7 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
 			swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 			negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 
-		sin_approx(c, inst->Prev, inst->I.DstReg,
+		sin_approx(c, inst, inst->I.DstReg,
 			swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 			constants);
 	} else if (inst->I.Opcode == RC_OPCODE_SIN) {
@@ -571,7 +571,7 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
 			swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 			negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 
-		sin_approx(c, inst->Prev, inst->I.DstReg,
+		sin_approx(c, inst, inst->I.DstReg,
 			swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 			constants);
 	} else {
@@ -589,12 +589,12 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
 		struct rc_dst_register dst = inst->I.DstReg;
 
 		dst.WriteMask = inst->I.DstReg.WriteMask & RC_MASK_X;
-		sin_approx(c, inst->Prev, dst,
+		sin_approx(c, inst, dst,
 			swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 			constants);
 
 		dst.WriteMask = inst->I.DstReg.WriteMask & RC_MASK_Y;
-		sin_approx(c, inst->Prev, dst,
+		sin_approx(c, inst, dst,
 			swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 			constants);
 	}
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 0fe32a5443..da5b7ba642 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -684,11 +684,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 	ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 	r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
-	if ((r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) ||
-	      ( !r300->radeon.radeonScreen->kernel_mm && (
-	    (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS400) ||
-	    (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
-	    (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420) ) ) ) {
+	if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
 		ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 	} else {
 		ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
@@ -697,6 +693,14 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 	r300->hw.zs.cmd[R300_ZS_CMD_0] =
 	    cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
+	if (is_r500) {
+		if (r300->radeon.radeonScreen->kernel_mm)
+			ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
+		else
+			ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
+		r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
+			cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
+	}
 
 	ALLOC_STATE(zstencil_format, always, 5, 0);
 	r300->hw.zstencil_format.cmd[0] =
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 1dadcc0a69..518d5cdbf4 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -234,6 +234,10 @@ typedef struct r300_context *r300ContextPtr;
 #define R300_ZS_CNTL_2		3
 #define R300_ZS_CMDSIZE		4
 
+#define R300_ZSB_CMD_0		0
+#define R300_ZSB_CNTL_0		1
+#define R300_ZSB_CMDSIZE	2
+
 #define R300_ZB_CMD_0		0
 #define R300_ZB_OFFSET		1
 #define R300_ZB_PITCH		2
@@ -343,6 +347,7 @@ struct r300_hw_state {
 	struct radeon_state_atom rb3d_aaresolve_ctl;	/* (4E88) */
 	struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;	/* (4E88) I saw it only written on RV350 hardware..  */
 	struct radeon_state_atom zs;	/* zstencil control (4F00) */
+	struct radeon_state_atom zsb;	/* zstencil bf */
 	struct radeon_state_atom zstencil_format;
 	struct radeon_state_atom zb;	/* z buffer (4F20) */
 	struct radeon_state_atom zb_depthclearvalue;	/* (4F28) */
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 98512d778e..b9ccd098dc 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -2313,6 +2313,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_Z_WRITE_ENABLE		 (1 << 2)
 #	define R300_Z_SIGNED_COMPARE		 (1 << 3)
 #	define R300_STENCIL_FRONT_BACK		 (1 << 4)
+#	define R400_ZSIGNED_MAGNITUDE		 (1 << 5)
+#	define R500_STENCIL_REFMASK_FRONT_BACK	 (1 << 6)
 
 #define R300_ZB_ZSTENCILCNTL                   0x4f04
 	/* functions */
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index d4c3ecee66..3060f49aaf 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -590,7 +590,9 @@ static void r300SetDepthState(GLcontext * ctx)
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
 
 	R300_STATECHANGE(r300, zs);
-	r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_STENCIL_ENABLE|R300_STENCIL_FRONT_BACK;
+	r300->hw.zs.cmd[R300_ZS_CNTL_0] &= (R300_STENCIL_ENABLE |
+					    R300_STENCIL_FRONT_BACK |
+					    R500_STENCIL_REFMASK_FRONT_BACK);
 	r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT);
 
 	if (ctx->Depth.Test) {
@@ -604,11 +606,16 @@ static void r300SetDepthState(GLcontext * ctx)
 
 static void r300CatchStencilFallback(GLcontext *ctx)
 {
+	r300ContextPtr rmesa = R300_CONTEXT(ctx);
 	const unsigned back = ctx->Stencil._BackFace;
 
-	if (ctx->Stencil._Enabled && (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back]
-		|| ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back]
-		|| ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])) {
+	if (rmesa->radeon.radeonScreen->kernel_mm &&
+	    (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)) {
+		r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE);
+	} else if (ctx->Stencil._Enabled &&
+		   (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back]
+		    || ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back]
+		    || ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])) {
 		r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_TRUE);
 	} else {
 		r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE);
@@ -915,11 +922,24 @@ static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face,
 	rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
 	    (flag << R300_S_BACK_FUNC_SHIFT);
 	rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask;
+
+	if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
+		rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R500_STENCIL_REFMASK_FRONT_BACK;
+		R300_STATECHANGE(rmesa, zsb);
+		refmask = ((ctx->Stencil.Ref[back] & 0xff) << R300_STENCILREF_SHIFT)
+			| ((ctx->Stencil.ValueMask[back] & 0xff) << R300_STENCILMASK_SHIFT);
+
+		rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] &=
+			~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) |
+			  (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT));
+		rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] |= refmask;
+	}
 }
 
 static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
 {
 	r300ContextPtr rmesa = R300_CONTEXT(ctx);
+	const unsigned back = ctx->Stencil._BackFace;
 
 	r300CatchStencilFallback(ctx);
 
@@ -931,6 +951,13 @@ static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
 	    (ctx->Stencil.
 	     WriteMask[0] & R300_STENCILREF_MASK) <<
 	     R300_STENCILWRITEMASK_SHIFT;
+	if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
+		R300_STATECHANGE(rmesa, zsb);
+		rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] |=
+			(ctx->Stencil.
+			 WriteMask[back] & R300_STENCILREF_MASK) <<
+			R300_STENCILWRITEMASK_SHIFT;
+	}
 }
 
 static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c
index d5e2cf9b14..8ad75fb5c0 100644
--- a/src/mesa/drivers/dri/r300/r300_vertprog.c
+++ b/src/mesa/drivers/dri/r300/r300_vertprog.c
@@ -203,6 +203,34 @@ static void t_inputs_outputs(struct r300_vertex_program_compiler * c)
 	}
 }
 
+/**
+ * The NV_vertex_program spec mandates that all registers be
+ * initialized to zero. We do this here unconditionally.
+ *
+ * \note We rely on dead-code elimination in the compiler.
+ */
+static void initialize_NV_registers(struct radeon_compiler * compiler)
+{
+	unsigned int reg;
+	struct rc_instruction * inst;
+
+	for(reg = 0; reg < 12; ++reg) {
+		inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
+		inst->I.Opcode = RC_OPCODE_MOV;
+		inst->I.DstReg.File = RC_FILE_TEMPORARY;
+		inst->I.DstReg.Index = reg;
+		inst->I.SrcReg[0].File = RC_FILE_NONE;
+		inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
+	}
+
+	inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
+	inst->I.Opcode = RC_OPCODE_ARL;
+	inst->I.DstReg.File = RC_FILE_ADDRESS;
+	inst->I.DstReg.Index = 0;
+	inst->I.DstReg.WriteMask = WRITEMASK_X;
+	inst->I.SrcReg[0].File = RC_FILE_NONE;
+	inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
+}
 
 static struct r300_vertex_program *build_program(GLcontext *ctx,
 						 struct r300_vertex_program_key *wanted_key,
@@ -234,6 +262,9 @@ static struct r300_vertex_program *build_program(GLcontext *ctx,
 
 	radeon_mesa_to_rc_program(&compiler.Base, &vp->Base->Base);
 
+	if (mesa_vp->IsNVProgram)
+		initialize_NV_registers(&compiler.Base);
+
 	rc_move_output(&compiler.Base, VERT_RESULT_PSIZ, VERT_RESULT_PSIZ, WRITEMASK_X);
 
 	if (vp->key.WPosAttr != FRAG_ATTRIB_MAX) {
diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h
index 250570f6b8..da4812d323 100644
--- a/src/mesa/drivers/dri/r300/radeon_context.h
+++ b/src/mesa/drivers/dri/r300/radeon_context.h
@@ -51,26 +51,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "radeon_screen.h"
 
-#if R200_MERGED
-extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
-
-#define FALLBACK( radeon, bit, mode ) do {			\
-   if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n",	\
-		     __FUNCTION__, bit, mode );			\
-   radeonFallback( (radeon)->glCtx, bit, mode );		\
-} while (0)
-#else
 #define FALLBACK( radeon, bit, mode ) fprintf(stderr, "%s:%s\n", __LINE__, __FILE__);
-#endif
 
 /* TCL fallbacks */
 extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
 
-#if R200_MERGED
-#define TCL_FALLBACK( ctx, bit, mode )	radeonTclFallback( ctx, bit, mode )
-#else
 #define TCL_FALLBACK( ctx, bit, mode )	;
-#endif
 
 
 #endif				/* __RADEON_CONTEXT_H__ */
diff --git a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c b/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c
index 1e8fc3de4e..fb9bb9ce91 100644
--- a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c
+++ b/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c
@@ -94,7 +94,6 @@ static rc_saturate_mode translate_saturate(unsigned int saturate)
 	default:
 	case SATURATE_OFF: return RC_SATURATE_NONE;
 	case SATURATE_ZERO_ONE: return RC_SATURATE_ZERO_ONE;
-	case SATURATE_PLUS_MINUS_ONE: return RC_SATURATE_MINUS_PLUS_ONE;
 	}
 }
 
@@ -189,13 +188,36 @@ void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * p
 	c->Program.InputsRead = program->InputsRead;
 	c->Program.OutputsWritten = program->OutputsWritten;
 
-	for(i = 0; i < program->Parameters->NumParameters; ++i) {
-		struct rc_constant constant;
+	int isNVProgram = 0;
 
-		constant.Type = RC_CONSTANT_EXTERNAL;
-		constant.Size = 4;
-		constant.u.External = i;
+	if (program->Target == GL_VERTEX_PROGRAM_ARB) {
+		struct gl_vertex_program * vp = (struct gl_vertex_program *) program;
+		isNVProgram = vp->IsNVProgram;
+	}
 
-		rc_constants_add(&c->Program.Constants, &constant);
+	if (isNVProgram) {
+		/* NV_vertex_program has a fixed-sized constant environment.
+		 * This could be handled more efficiently for programs that
+		 * do not use relative addressing.
+		 */
+		for(i = 0; i < 96; ++i) {
+			struct rc_constant constant;
+
+			constant.Type = RC_CONSTANT_EXTERNAL;
+			constant.Size = 4;
+			constant.u.External = i;
+
+			rc_constants_add(&c->Program.Constants, &constant);
+		}
+	} else {
+		for(i = 0; i < program->Parameters->NumParameters; ++i) {
+			struct rc_constant constant;
+
+			constant.Type = RC_CONSTANT_EXTERNAL;
+			constant.Size = 4;
+			constant.u.External = i;
+
+			rc_constants_add(&c->Program.Constants, &constant);
+		}
 	}
 }
diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile
index d925a2dfe3..36bf773c05 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -65,8 +65,7 @@ DRIVER_SOURCES = \
 
 C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
 
-DRIVER_DEFINES = -DCOMPILE_R600 -DR200_MERGED=0 \
-	-DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R600 \
+DRIVER_DEFINES = -DRADEON_R600 \
 #	-DRADEON_BO_TRACK \
 	-Wall
 
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 07a7bcf11f..f8fd9c13d7 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -385,9 +385,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 
 	if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) {
 		radeon_warning("disabling 3D acceleration\n");
-#if R200_MERGED
-		FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1);
-#endif
 	}
 
 	return GL_TRUE;
diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index 8ae05a301c..c59df7505a 100644
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -51,6 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r700_chip.h"
 #include "r600_tex.h"
 #include "r700_oglprog.h"
+#include "r700_vertprog.h"
 
 struct r600_context;
 typedef struct r600_context context_t;
@@ -155,6 +156,8 @@ struct r600_context {
 
 	struct r600_hw_state atoms;
 
+	struct r700_vertex_program *selected_vp;
+
 	/* Vertex buffers
 	 */
 	GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
diff --git a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h
index 9d5aa3c7e4..edd85b0fac 100644
--- a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h
+++ b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h
@@ -1366,6 +1366,7 @@ enum {
 	DB_DEPTH_INFO__READ_SIZE_bit                      = 1 << 3,
 	DB_DEPTH_INFO__ARRAY_MODE_mask                    = 0x0f << 15,
 	DB_DEPTH_INFO__ARRAY_MODE_shift                   = 15,
+	    ARRAY_1D_TILED_THIN1                          = 0x02,
 	    ARRAY_2D_TILED_THIN1                          = 0x04,
 	TILE_SURFACE_ENABLE_bit                           = 1 << 25,
 	TILE_COMPACT_bit                                  = 1 << 26,
@@ -1449,6 +1450,7 @@ enum {
 	CB_COLOR0_INFO__ARRAY_MODE_shift                  = 8,
 	    ARRAY_LINEAR_GENERAL                          = 0x00,
 	    ARRAY_LINEAR_ALIGNED                          = 0x01,
+/*	    ARRAY_1D_TILED_THIN1                          = 0x02, */
 /* 	    ARRAY_2D_TILED_THIN1                          = 0x04, */
 	NUMBER_TYPE_mask                                  = 0x07 << 12,
 	NUMBER_TYPE_shift                                 = 12,
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index fff6e74386..7d7e77d355 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -69,7 +69,7 @@ void r600UpdateTextureState(GLcontext * ctx)
 	for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) {
 		texUnit = &ctx->Texture.Unit[unit];
 		t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
-
+		r700->textures[unit] = NULL;
 		if (texUnit->_ReallyEnabled) {
 			if (!t)
 				continue;
@@ -608,6 +608,11 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
 	int firstlevel = t->mt ? t->mt->firstLevel : 0;
 	GLuint uTexelPitch, row_align;
 
+	if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
+	    t->image_override &&
+	    t->bo)
+		return;
+
 	firstImage = t->base.Image[0][firstlevel];
 
 	if (!t->image_override) {
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 2d8480daaf..efeccb25f1 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1149,41 +1149,49 @@ GLboolean tex_dst(r700_AssemblerBase *pAsm)
 GLboolean tex_src(r700_AssemblerBase *pAsm)
 {
     struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
- 
+
     GLboolean bValidTexCoord = GL_FALSE;
 
-    switch (pILInst->SrcReg[0].File)
-    {
+    switch (pILInst->SrcReg[0].File) {
+    case PROGRAM_CONSTANT:
+    case PROGRAM_LOCAL_PARAM:
+    case PROGRAM_ENV_PARAM:
+    case PROGRAM_STATE_VAR:
+	    bValidTexCoord = GL_TRUE;
+	    setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
+	    pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
+	    pAsm->S[0].src.reg   = pAsm->aArgSubst[1];
+	    break;
     case PROGRAM_TEMPORARY:
-        bValidTexCoord = GL_TRUE;
-
-        pAsm->S[0].src.reg   = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number;
-        pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
-
-        break;
+	    bValidTexCoord = GL_TRUE;
+	    pAsm->S[0].src.reg   = pILInst->SrcReg[0].Index +
+		    pAsm->starting_temp_register_number;
+	    pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
+       break;
     case PROGRAM_INPUT:
-        switch (pILInst->SrcReg[0].Index)
-        {
-        case FRAG_ATTRIB_COL0:
-        case FRAG_ATTRIB_COL1:
-        case FRAG_ATTRIB_TEX0:
-        case FRAG_ATTRIB_TEX1:
-        case FRAG_ATTRIB_TEX2:
-        case FRAG_ATTRIB_TEX3:
-        case FRAG_ATTRIB_TEX4:
-        case FRAG_ATTRIB_TEX5:
-        case FRAG_ATTRIB_TEX6:
-        case FRAG_ATTRIB_TEX7:
-            bValidTexCoord = GL_TRUE;
-
-            pAsm->S[0].src.reg   = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
-            pAsm->S[0].src.rtype = SRC_REG_INPUT;
-        }
-        break;
+	    switch (pILInst->SrcReg[0].Index)
+	    {
+	    case FRAG_ATTRIB_COL0:
+	    case FRAG_ATTRIB_COL1:
+	    case FRAG_ATTRIB_TEX0:
+	    case FRAG_ATTRIB_TEX1:
+	    case FRAG_ATTRIB_TEX2:
+	    case FRAG_ATTRIB_TEX3:
+	    case FRAG_ATTRIB_TEX4:
+	    case FRAG_ATTRIB_TEX5:
+	    case FRAG_ATTRIB_TEX6:
+	    case FRAG_ATTRIB_TEX7:
+		    bValidTexCoord = GL_TRUE;
+		    pAsm->S[0].src.reg   =
+			    pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
+		    pAsm->S[0].src.rtype = SRC_REG_INPUT;
+		    break;
+	    }
+	    break;
     }
 
     if(GL_TRUE == bValidTexCoord)
-    { 
+    {
         setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
     }
     else
@@ -1201,7 +1209,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
     pAsm->S[0].src.negy = (pILInst->SrcReg[0].Negate >> 1) & 0x1;
     pAsm->S[0].src.negz = (pILInst->SrcReg[0].Negate >> 2) & 0x1;
     pAsm->S[0].src.negw = (pILInst->SrcReg[0].Negate >> 3) & 0x1;
-     
+
     return GL_TRUE;
 }
 
@@ -2202,7 +2210,9 @@ GLboolean next_ins(r700_AssemblerBase *pAsm)
 {
     struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
 
-    if( GL_TRUE == IsTex(pILInst->Opcode) )
+    if( GL_TRUE == IsTex(pILInst->Opcode) &&
+        /* handle const moves to temp register */ 
+        !(pAsm->D.dst.opcode == SQ_OP2_INST_MOV) )
     {
 	    if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) {
 		    if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) 
@@ -3374,28 +3384,31 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
     case PROGRAM_ENV_PARAM:
     case PROGRAM_STATE_VAR:
         src_const = GL_TRUE;
+        break;
     case PROGRAM_TEMPORARY:
     case PROGRAM_INPUT:
+    default:
         src_const = GL_FALSE;
+	break;
     }
 
-    if (GL_TRUE == src_const) 
+    if (GL_TRUE == src_const)
     {
-        radeon_error("TODO: Texture coordinates from a constant register not supported.\n");
-        return GL_FALSE;
+	    if ( GL_FALSE == mov_temp(pAsm, 0) )
+		    return GL_FALSE;
     }
 
-    switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) 
+    switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)
     {
         case OPCODE_TEX:
-            pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;            
+            pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
             break;
-        case OPCODE_TXB:            
+        case OPCODE_TXB:
             radeon_error("do not support TXB yet\n");
             return GL_FALSE;
             break;
-        case OPCODE_TXP:            
-            /* TODO : tex proj version : divid first 3 components by 4th */ 
+        case OPCODE_TXP:
+            /* TODO : tex proj version : divid first 3 components by 4th */
             pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
             break;
         default:
@@ -3418,13 +3431,13 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
     {
         return GL_FALSE;
     }
- 
+
     if( GL_FALSE == tex_src(pAsm) )
     {
         return GL_FALSE;
     }
 
-    if ( GL_FALSE == next_ins(pAsm) ) 
+    if ( GL_FALSE == next_ins(pAsm) )
     {
         return GL_FALSE;
     }
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 37bff56f5a..06d7e9c9ab 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -52,38 +52,40 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
 	radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
 	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-		radeonTexObj *t = r700->textures[i];
-		if (t) {
-			if (!t->image_override)
-				bo = t->mt->bo;
-			else
-				bo = t->bo;
-			if (bo) {
-
-				r700SyncSurf(context, bo,
-					     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
-					     0, TC_ACTION_ENA_bit);
-
-				BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
-				R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-				R600_OUT_BATCH(i * 7);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
-				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
-				R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
-						     bo,
-						     0,
-						     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-				R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
-						     bo,
-						     r700->textures[i]->SQ_TEX_RESOURCE3,
-						     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-				END_BATCH();
-				COMMIT_BATCH();
+		if (ctx->Texture.Unit[i]._ReallyEnabled) {
+			radeonTexObj *t = r700->textures[i];
+			if (t) {
+				if (!t->image_override)
+					bo = t->mt->bo;
+				else
+					bo = t->bo;
+				if (bo) {
+
+					r700SyncSurf(context, bo,
+						     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
+						     0, TC_ACTION_ENA_bit);
+
+					BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
+					R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+					R600_OUT_BATCH(i * 7);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
+					R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
+					R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
+							     bo,
+							     0,
+							     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+					R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
+							     bo,
+							     r700->textures[i]->SQ_TEX_RESOURCE3,
+							     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+					END_BATCH();
+					COMMIT_BATCH();
+				}
 			}
 		}
 	}
@@ -98,16 +100,18 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at
 	radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
 	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-		radeonTexObj *t = r700->textures[i];
-		if (t) {
-			BEGIN_BATCH_NO_AUTOSTATE(5);
-			R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-			R600_OUT_BATCH(i * 3);
-			R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
-			R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
-			R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
-			END_BATCH();
-			COMMIT_BATCH();
+		if (ctx->Texture.Unit[i]._ReallyEnabled) {
+			radeonTexObj *t = r700->textures[i];
+			if (t) {
+				BEGIN_BATCH_NO_AUTOSTATE(5);
+				R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
+				R600_OUT_BATCH(i * 3);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
+				END_BATCH();
+				COMMIT_BATCH();
+			}
 		}
 	}
 }
@@ -121,16 +125,18 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom
 	radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
 	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-		radeonTexObj *t = r700->textures[i];
-		if (t) {
-			BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
-			R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
-			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
-			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
-			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
-			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
-			END_BATCH();
-			COMMIT_BATCH();
+		if (ctx->Texture.Unit[i]._ReallyEnabled) {
+			radeonTexObj *t = r700->textures[i];
+			if (t) {
+				BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
+				R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
+				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
+				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
+				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
+				R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
+				END_BATCH();
+				COMMIT_BATCH();
+			}
 		}
 	}
 }
@@ -205,8 +211,7 @@ static void r700SetupVTXConstants(GLcontext  * ctx,
 void r700SetupStreams(GLcontext *ctx)
 {
     context_t         *context = R700_CONTEXT(ctx);
-     struct r700_vertex_program *vpc
-             = (struct r700_vertex_program *)ctx->VertexProgram._Current;
+    struct r700_vertex_program *vp = context->selected_vp;
     TNLcontext *tnl = TNL_CONTEXT(ctx);
     struct vertex_buffer *vb = &tnl->vb;
     unsigned int i, j = 0;
@@ -215,7 +220,7 @@ void r700SetupStreams(GLcontext *ctx)
     R600_STATECHANGE(context, vtx);
 
     for(i=0; i<VERT_ATTRIB_MAX; i++) {
-	    if(vpc->mesa_program.Base.InputsRead & (1 << i)) {
+	    if(vp->mesa_program->Base.InputsRead & (1 << i)) {
 		    rcommon_emit_vector(ctx,
 					&context->radeon.tcl.aos[j],
 					vb->AttribPtr[i]->data,
@@ -231,8 +236,7 @@ void r700SetupStreams(GLcontext *ctx)
 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
     context_t         *context = R700_CONTEXT(ctx);
-    struct r700_vertex_program *vpc
-             = (struct r700_vertex_program *)ctx->VertexProgram._Current;
+    struct r700_vertex_program *vp = context->selected_vp;
     unsigned int i, j = 0;
     BATCH_LOCALS(&context->radeon);
 	radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
@@ -252,7 +256,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
     COMMIT_BATCH();
 
     for(i=0; i<VERT_ATTRIB_MAX; i++) {
-	    if(vpc->mesa_program.Base.InputsRead & (1 << i)) {
+	    if(vp->mesa_program->Base.InputsRead & (1 << i)) {
 		    /* currently aos are packed */
 		    r700SetupVTXConstants(ctx,
 					  i,
@@ -347,7 +351,7 @@ static void r700SetDepthTarget(context_t *context)
         SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
                      DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
     }
-    SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
+    SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
              DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
     /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
 }
@@ -1176,9 +1180,11 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
 	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-		radeonTexObj *t = r700->textures[i];
-		if (t)
-			count++;
+		if (ctx->Texture.Unit[i]._ReallyEnabled) {
+			radeonTexObj *t = r700->textures[i];
+			if (t)
+				count++;
+		}
 	}
 	radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
 	return count * 31;
diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c
index 3c8c1fd7a3..5290ef31be 100644
--- a/src/mesa/drivers/dri/r600/r700_oglprog.c
+++ b/src/mesa/drivers/dri/r600/r700_oglprog.c
@@ -46,7 +46,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx,
 {
 	struct gl_program *pProgram = NULL;
 
-    struct r700_vertex_program *vp;
+    struct r700_vertex_program_cont *vpc;
 	struct r700_fragment_program *fp;
 
 	radeon_print(RADEON_SHADER, RADEON_VERBOSE,
@@ -56,16 +56,11 @@ static struct gl_program *r700NewProgram(GLcontext * ctx,
     {
     case GL_VERTEX_STATE_PROGRAM_NV:
     case GL_VERTEX_PROGRAM_ARB:	    
-        vp       = CALLOC_STRUCT(r700_vertex_program);
+        vpc       = CALLOC_STRUCT(r700_vertex_program_cont);
 	    pProgram = _mesa_init_vertex_program(ctx, 
-                                             &vp->mesa_program,
+                                             &vpc->mesa_program,
 					                         target, 
                                              id);
-        vp->translated = GL_FALSE;
-        vp->loaded     = GL_FALSE;
- 
-        vp->shaderbo   = NULL;
-
 	    break;
     case GL_FRAGMENT_PROGRAM_NV:
     case GL_FRAGMENT_PROGRAM_ARB:
@@ -89,7 +84,8 @@ static struct gl_program *r700NewProgram(GLcontext * ctx,
 
 static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog)
 {
-    struct r700_vertex_program   * vp;
+    struct r700_vertex_program_cont   * vpc;
+    struct r700_vertex_program *vp, *tmp;
     struct r700_fragment_program * fp;
 
 	radeon_print(RADEON_SHADER, RADEON_VERBOSE,
@@ -99,14 +95,20 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog)
     {
     case GL_VERTEX_STATE_PROGRAM_NV:
     case GL_VERTEX_PROGRAM_ARB:	    
-        vp = (struct r700_vertex_program*)prog;
-        /* Release DMA region */
-
-        r600DeleteShader(ctx, vp->shaderbo);
-
-        /* Clean up */
-        Clean_Up_Assembler(&(vp->r700AsmCode));
-        Clean_Up_Shader(&(vp->r700Shader));
+        vpc = (struct r700_vertex_program_cont*)prog;
+        vp = vpc->progs;
+	while (vp) {
+		tmp = vp->next;
+		/* Release DMA region */
+	 
+	        r600DeleteShader(ctx, vp->shaderbo);
+
+	        /* Clean up */
+	        Clean_Up_Assembler(&(vp->r700AsmCode));
+	        Clean_Up_Shader(&(vp->r700Shader));
+		_mesa_free(vp);
+		vp = tmp;
+	}
 	    break;
     case GL_FRAGMENT_PROGRAM_NV:
     case GL_FRAGMENT_PROGRAM_ARB:
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 3566bf3ca7..b1c3648ca5 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -319,14 +319,13 @@ static GLuint r700PredictRenderSize(GLcontext* ctx)
 {
     context_t *context = R700_CONTEXT(ctx);
     TNLcontext *tnl = TNL_CONTEXT(ctx);
-    struct r700_vertex_program *vpc
-        = (struct r700_vertex_program *)ctx->VertexProgram._Current;
+    struct r700_vertex_program *vp = context->selected_vp;
     struct vertex_buffer *vb = &tnl->vb;
     GLboolean flushed;
     GLuint dwords, i;
     GLuint state_size;
     /* pre calculate aos count so state prediction works */
-    context->radeon.tcl.aos_count = _mesa_bitcount(vpc->mesa_program.Base.InputsRead);
+    context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead);
 
     dwords = PRE_EMIT_STATE_BUFSZ;
     for (i = 0; i < vb->PrimitiveCount; i++)
@@ -365,7 +364,6 @@ static GLboolean r700RunRender(GLcontext * ctx,
     /* mark vtx as dirty since it changes per-draw */
     R600_STATECHANGE(context, vtx);
 
-    r700UpdateShaders(ctx);
     r700SetScissor(context);
     r700SetupVertexProgram(ctx);
     r700SetupFragmentProgram(ctx);
@@ -427,7 +425,10 @@ static GLboolean r700RunTCLRender(GLcontext * ctx,  /*----------------------*/
 
     /* TODO : sw fallback */
 
+    /* Need shader bo's setup before bo check */
+    r700UpdateShaders(ctx);
     /**
+
     * Ensure all enabled and complete textures are uploaded along with any buffers being used.
     */
     if(!r600ValidateBuffers(ctx))
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 93b4ebfdb9..fc0b511684 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -845,9 +845,9 @@ static void r700PointSize(GLcontext * ctx, GLfloat size)
 	size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
 
 	/* format is 12.4 fixed point */
-	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
+	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
 		 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
-	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
+	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
 		 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
 
 }
@@ -862,11 +862,11 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
 	/* format is 12.4 fixed point */
 	switch (pname) {
 	case GL_POINT_SIZE_MIN:
-		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
+		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
 			 MIN_SIZE_shift, MIN_SIZE_mask);
 		break;
 	case GL_POINT_SIZE_MAX:
-		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
+		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
 			 MAX_SIZE_shift, MAX_SIZE_mask);
 		break;
 	case GL_POINT_DISTANCE_ATTENUATION:
@@ -1130,20 +1130,25 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 	GLfloat constant = units;
+	GLchar depth = 0;
+
+	R600_STATECHANGE(context, poly);
 
 	switch (ctx->Visual.depthBits) {
 	case 16:
 		constant *= 4.0;
+		depth = -16;
 		break;
 	case 24:
 		constant *= 2.0;
+		depth = -24;
 		break;
 	}
 
 	factor *= 12.0;
-
-	R600_STATECHANGE(context, poly);
-
+	SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
+		 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
+	//r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
 	r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
 	r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
 	r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
@@ -1280,8 +1285,8 @@ void r700SetScissor(context_t *context) //---------------
 		if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
 			x1 = 0;
 			y1 = 0;
-			x2 = rrb->base.Width - 1;
-			y2 = rrb->base.Height - 1;
+			x2 = rrb->base.Width;
+			y2 = rrb->base.Height;
 		} else {
 			x1 = rrb->dPriv->x;
 			y1 = rrb->dPriv->y;
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index d107f99e7b..9ee26286d9 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -35,12 +35,14 @@
 #include "main/mtypes.h"
 
 #include "tnl/t_context.h"
+#include "shader/program.h"
 #include "shader/prog_parameter.h"
 #include "shader/prog_statevars.h"
 
 #include "radeon_debug.h"
 #include "r600_context.h"
 #include "r600_cmdbuf.h"
+#include "shader/programopt.c"
 
 #include "r700_debug.h"
 #include "r700_vertprog.h"
@@ -258,28 +260,59 @@ GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp,
     return GL_TRUE;
 }
 
-GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp,
-							   struct gl_vertex_program   *mesa_vp)
+struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
+						struct gl_vertex_program *mesa_vp)
 {
+	context_t *context = R700_CONTEXT(ctx);
+	struct r700_vertex_program *vp;
+	TNLcontext *tnl = TNL_CONTEXT(ctx);
+	struct vertex_buffer *vb = &tnl->vb;
+	unsigned int unBit;
+	unsigned int i;
+
+	vp = _mesa_calloc(sizeof(*vp));
+	vp->mesa_program = (struct gl_vertex_program *)_mesa_clone_program(ctx, &mesa_vp->Base);
+
+	if (mesa_vp->IsPositionInvariant)
+	{
+                _mesa_insert_mvp_code(ctx, vp->mesa_program);
+        }
+
+	for(i=0; i<VERT_ATTRIB_MAX; i++)
+	{
+		unBit = 1 << i;
+		if(vp->mesa_program->Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */
+		{
+			vp->aos_desc[i].size   = vb->AttribPtr[i]->size;
+			vp->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/
+			vp->aos_desc[i].type   = GL_FLOAT;
+		}
+	}
+	
+	if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+	{
+		vp->r700AsmCode.bR6xx = 1;
+	}
+
 	//Init_Program
 	Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) );
-	Map_Vertex_Program( vp, mesa_vp );
+	Map_Vertex_Program( vp, vp->mesa_program );
 
-	if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, mesa_vp))
+	if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, vp->mesa_program))
 	{
-		return GL_FALSE;
+		return NULL;
     }
 
-	if(GL_FALSE == AssembleInstr(mesa_vp->Base.NumInstructions,
-                                 &(mesa_vp->Base.Instructions[0]), 
+	if(GL_FALSE == AssembleInstr(vp->mesa_program->Base.NumInstructions,
+                                 &(vp->mesa_program->Base.Instructions[0]), 
                                  &(vp->r700AsmCode)) )
 	{
-		return GL_FALSE;
+		return NULL;
 	} 
 
-    if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), mesa_vp->Base.OutputsWritten) )
+    if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) )
     {
-        return GL_FALSE;
+        return NULL;
     }
 
     vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0 
@@ -289,72 +322,82 @@ GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp,
 
     vp->translated = GL_TRUE;
 
-	return GL_TRUE;
+	return vp;
 }
 
 void r700SelectVertexShader(GLcontext *ctx)
 {
     context_t *context = R700_CONTEXT(ctx);
-    struct r700_vertex_program *vpc
-             = (struct r700_vertex_program *)ctx->VertexProgram._Current;
+    struct r700_vertex_program_cont *vpc;
+    struct r700_vertex_program *vp;
     TNLcontext *tnl = TNL_CONTEXT(ctx);
     struct vertex_buffer *vb = &tnl->vb;
     unsigned int unBit;
     unsigned int i;
+    GLboolean match;
+    GLbitfield InputsRead;
 
-    if (context->radeon.NewGLState & (_NEW_PROGRAM_CONSTANTS|_NEW_PROGRAM))
-    {
-	vpc->needUpdateVF = 1;
-    }
+    vpc = (struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
 
-    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+    InputsRead = vpc->mesa_program.Base.InputsRead;
+    if (vpc->mesa_program.IsPositionInvariant)
     {
-        vpc->r700AsmCode.bR6xx = 1;
-    }
-
+	InputsRead |= VERT_BIT_POS;
+    } 
+    
+    for (vp = vpc->progs; vp; vp = vp->next)
+    {
+	match = GL_TRUE;	
 	for(i=0; i<VERT_ATTRIB_MAX; i++)
 	{
 		unBit = 1 << i;
-		if(vpc->mesa_program.Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */
+		if(InputsRead & unBit)
 		{
-			vpc->aos_desc[i].size   = vb->AttribPtr[i]->size;
-			vpc->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/
-			vpc->aos_desc[i].type   = GL_FLOAT;
+			if (vp->aos_desc[i].size != vb->AttribPtr[i]->size)
+				match = GL_FALSE;
+				break;
 		}
 	}
-
-	if(GL_FALSE == vpc->translated) {
-		r700TranslateVertexShader(vpc, &(vpc->mesa_program) );
+	if (match) 
+	{
+		context->selected_vp = vp;
+		return;
 	}
+    }
+
+    vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program) );
+    if(!vp)
+    {
+	radeon_error("Failed to translate vertex shader. \n");
+	return;
+    }
+    vp->next = vpc->progs;
+    vpc->progs = vp;
+    context->selected_vp = vp;
+    return;
 }
 
 void * r700GetActiveVpShaderBo(GLcontext * ctx)
 {
-    struct r700_vertex_program *vp
-             = (struct r700_vertex_program *)ctx->VertexProgram._Current;
+    context_t *context = R700_CONTEXT(ctx);
+    struct r700_vertex_program *vp = context->selected_vp;;
 
-    return vp->shaderbo;
+    if (vp)
+	return vp->shaderbo;
+    else
+	return NULL;
 }
 
 GLboolean r700SetupVertexProgram(GLcontext * ctx)
 {
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-    struct r700_vertex_program *vp
-             = (struct r700_vertex_program *)ctx->VertexProgram._Current;
+    struct r700_vertex_program *vp = context->selected_vp;
 
     struct gl_program_parameter_list *paramList;
     unsigned int unNumParamData;
     unsigned int ui;
 
-    if (vp->needUpdateVF)
-    {
-	vp->loaded = GL_FALSE;
-	vp->r700Shader.bNeedsAssembly = GL_TRUE;
-	Process_Vertex_Program_Vfetch_Instructions(vp, &(vp->mesa_program));
-	r600DeleteShader(ctx, vp->shaderbo);
-    }
-
     if(GL_FALSE == vp->loaded)
     {
 	    if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
@@ -410,7 +453,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
     */
 
     /* sent out shader constants. */
-    paramList = vp->mesa_program.Base.Parameters;
+    paramList = vp->mesa_program->Base.Parameters;
 
     if(NULL != paramList) {
 	    _mesa_load_state_parameters(ctx, paramList);
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h
index e2e65021fd..c48764c43b 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.h
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.h
@@ -43,7 +43,7 @@ typedef struct ArrayDesc //TEMP
 
 struct r700_vertex_program 
 {
-    struct gl_vertex_program mesa_program; /* Must be first */
+    struct gl_vertex_program *mesa_program; /* Must be first */
 
     struct r700_vertex_program *next;
 
@@ -59,6 +59,13 @@ struct r700_vertex_program
     ArrayDesc              aos_desc[VERT_ATTRIB_MAX];
 };
 
+struct r700_vertex_program_cont
+{
+    struct gl_vertex_program mesa_program;
+
+    struct r700_vertex_program *progs;
+};
+
 //Internal
 unsigned int Map_Vertex_Output(r700_AssemblerBase       *pAsm, 
 			       struct gl_vertex_program *mesa_vp,
@@ -74,7 +81,7 @@ void Map_Vertex_Program(struct r700_vertex_program *vp,
 GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp,
 					   struct gl_vertex_program   *mesa_vp);
 
-GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp,
+struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
 				    struct gl_vertex_program   *mesa_vp);
 
 /* Interface */
diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile
index 1f286776b5..b1efc72872 100644
--- a/src/mesa/drivers/dri/radeon/Makefile
+++ b/src/mesa/drivers/dri/radeon/Makefile
@@ -47,8 +47,7 @@ C_SOURCES = \
 	$(DRIVER_SOURCES) \
 	$(CS_SOURCES)
 
-DRIVER_DEFINES = -DRADEON_COMMON=0 \
-				 -Wall
+DRIVER_DEFINES = -DRADEON_R100 -Wall
 
 DRI_LIB_DEPS += $(RADEON_LDFLAGS)
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index e53eb0904d..264392b327 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -1234,7 +1234,9 @@ int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller)
 	UNLOCK_HARDWARE(rmesa);
 
 	if (ret) {
-		fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret);
+		fprintf(stderr, "drmRadeonCmdBuffer: %d. Kernel failed to "
+				"parse or rejected command stream. See dmesg "
+				"for more info.\n", ret);
 		_mesa_exit(ret);
 	}
 
@@ -1343,5 +1345,5 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n,
 
 void radeonUserClear(GLcontext *ctx, GLuint mask)
 {
-   _mesa_meta_clear(ctx, mask);
+   _mesa_meta_Clear(ctx, mask);
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 71ee06d9a7..1c53c04da7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -47,7 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "swrast_setup/swrast_setup.h"
 #include "tnl/tnl.h"
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+#if defined(RADEON_R600)
 #include "r600_context.h"
 #endif
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_debug.c b/src/mesa/drivers/dri/radeon/radeon_debug.c
index a1ed39683f..413000b6c0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_debug.c
+++ b/src/mesa/drivers/dri/radeon/radeon_debug.c
@@ -32,11 +32,14 @@
 #include "radeon_debug.h"
 #include "radeon_common_context.h"
 
+#include <stdarg.h>
+#include <stdio.h>
+
 static const struct dri_debug_control debug_control[] = {
 	{"fall", RADEON_FALLBACKS},
 	{"tex", RADEON_TEXTURE},
 	{"ioctl", RADEON_IOCTL},
-	{"verts", RADEON_RENDER},
+	{"verts", RADEON_VERTS},
 	{"render", RADEON_RENDER},
 	{"swrender", RADEON_SWRENDER},
 	{"state", RADEON_STATE},
@@ -85,10 +88,10 @@ void _radeon_debug_remove_indent(void)
 	}
 }
 
-extern void _radeon_print(const radeon_debug_type_t type,
+void _radeon_print(const radeon_debug_type_t type,
 	   const radeon_debug_level_t level,
 	   const char* message,
-	   va_list values)
+	   ...)
 {
 	GET_CURRENT_CONTEXT(ctx);
 	if (ctx) {
@@ -97,5 +100,8 @@ extern void _radeon_print(const radeon_debug_type_t type,
 		if (radeon->debug.indent_depth)
 			fprintf(stderr, "%s", radeon->debug.indent);
 	}
+	va_list values;
+	va_start( values, message );
 	vfprintf(stderr, message, values);
+	va_end( values );
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_debug.h b/src/mesa/drivers/dri/radeon/radeon_debug.h
index 132e27351d..26da31c1c4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_debug.h
+++ b/src/mesa/drivers/dri/radeon/radeon_debug.h
@@ -30,8 +30,7 @@
 #ifndef RADEON_DEBUG_H_INCLUDED
 #define RADEON_DEBUG_H_INCLUDED
 
-#include <stdarg.h>
-#include <stdio.h>
+#include <stdlib.h>
 
 typedef enum radeon_debug_levels {
 	RADEON_CRITICAL  = 0, /* Only errors */
@@ -102,57 +101,36 @@ static inline int radeon_is_debug_enabled(const radeon_debug_type_t type,
 extern void _radeon_print(const radeon_debug_type_t type,
 	   const radeon_debug_level_t level,
 	   const char* message,
-	   va_list values);
-/**
- * Format attribute requires declaration for setting it. Don't ask me why!
- */
-static inline void radeon_print(const radeon_debug_type_t type,
-	   const radeon_debug_level_t level,
-	   const char* message,
-	   ...) __attribute__((format(printf,3,4)));
-
+	   ...)  __attribute__((format(printf,3,4)));
 /**
  * Print out debug message if channel specified by type is enabled
  * and compile time debugging level is at least as high as level parameter
  */
-static inline void radeon_print(const radeon_debug_type_t type,
-	   const radeon_debug_level_t level,
-	   const char* message,
-	   ...)
-{
-	/* Compile out if level of message is too high */
-	if (radeon_is_debug_enabled(type, level)) {
-
-		va_list values;
-		va_start( values, message );
-		_radeon_print(type, level, message, values);
-		va_end( values );
-	}
-}
+#define radeon_print(type, level, message, ...) do {		\
+	const radeon_debug_level_t _debug_level = (level);	\
+	const radeon_debug_type_t _debug_type = (type);		\
+	/* Compile out if level of message is too high */	\
+	if (radeon_is_debug_enabled(type, level)) {		\
+		_radeon_print(_debug_type, _debug_level,	\
+			(message), ## __VA_ARGS__);		\
+	}							\
+} while(0)
 
-static inline void radeon_error(const char* message, ...)  __attribute__((format(printf,1,2)));
 /**
  * printf style function for writing error messages.
  */
-static inline void radeon_error(const char* message, ...)
-{
-       va_list values;
-       va_start( values, message );
-       radeon_print(RADEON_GENERAL, RADEON_CRITICAL, message, values);
-       va_end( values );
-}
+#define radeon_error(message, ...) do {				\
+	radeon_print(RADEON_GENERAL, RADEON_CRITICAL,		\
+		(message), ## __VA_ARGS__);			\
+} while(0)
 
-static inline void radeon_warning(const char* message, ...)  __attribute__((format(printf,1,2)));
 /**
  * printf style function for writing warnings.
  */
-static inline void radeon_warning(const char* message, ...)
-{
-       va_list values;
-       va_start( values, message );
-       radeon_print(RADEON_GENERAL, RADEON_IMPORTANT, message, values);
-       va_end( values );
-}
+#define radeon_warning(message, ...) do {			\
+	radeon_print(RADEON_GENERAL, RADEON_IMPORTANT,		\
+		(message), ## __VA_ARGS__);			\
+} while(0)
 
 extern void radeon_init_debug(void);
 extern void _radeon_debug_add_indent(void);
@@ -171,21 +149,22 @@ static inline void radeon_debug_remove_indent(void)
        }
 }
 
+
 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
    with other compilers ... GLUE!
 */
-#define WARN_ONCE(a, ...)      { \
-       static int warn##__LINE__=1; \
-       if(warn##__LINE__){ \
+#define WARN_ONCE(a, ...)      do { \
+       static int __warn_once=1; \
+       if(__warn_once){ \
                radeon_warning("*********************************WARN_ONCE*********************************\n"); \
                radeon_warning("File %s function %s line %d\n", \
                        __FILE__, __FUNCTION__, __LINE__); \
                radeon_warning(  (a), ## __VA_ARGS__);\
                radeon_warning("***************************************************************************\n"); \
-               warn##__LINE__=0;\
+               __warn_once=0;\
                } \
-       }
+       } while(0)
 
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 2eefa3f2b1..c6edbae9a1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -207,7 +207,6 @@ again_alloc:
 		   counter on unused buffers for later freeing them from
 		   begin of list */
 		dma_bo = last_elem(&rmesa->dma.free);
-		assert(dma_bo->bo->cref == 1);
 		remove_from_list(dma_bo);
 		insert_at_head(&rmesa->dma.reserved, dma_bo);
 	}
@@ -263,7 +262,7 @@ void radeonAllocDmaRegion(radeonContextPtr rmesa,
 
 void radeonFreeDmaRegions(radeonContextPtr rmesa)
 {
-	struct radeon_dma_bo *dma_bo = CALLOC_STRUCT(radeon_dma_bo);
+	struct radeon_dma_bo *dma_bo;
 	struct radeon_dma_bo *temp;
 	if (RADEON_DEBUG & RADEON_DMA)
 		fprintf(stderr, "%s\n", __FUNCTION__);
@@ -307,6 +306,10 @@ static int radeon_bo_is_idle(struct radeon_bo* bo)
 		WARN_ONCE("Your libdrm or kernel doesn't have support for busy query.\n"
 			"This may cause small performance drop for you.\n");
 	}
+	/* Protect against bug in legacy bo handling that causes bos stay
+	 * referenced even after they should be freed */
+	if (bo->cref != 1)
+		return 0;
 	return ret != -EBUSY;
 }
 
@@ -343,7 +346,9 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa)
 	foreach_s(dma_bo, temp, &rmesa->dma.wait) {
 		if (dma_bo->expire_counter == time) {
 			WARN_ONCE("Leaking dma buffer object!\n");
-			radeon_bo_unref(dma_bo->bo);
+			/* force free of buffer so we don't realy start
+			 * leaking stuff now*/
+			while ((dma_bo->bo = radeon_bo_unref(dma_bo->bo))) {}
 			remove_from_list(dma_bo);
 			FREE(dma_bo);
 			continue;
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index d83b166742..7ac53ec0ca 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -583,7 +583,7 @@ void radeon_fbo_init(struct radeon_context *radeon)
   radeon->glCtx->Driver.FinishRenderTexture = radeon_finish_render_texture;
   radeon->glCtx->Driver.ResizeBuffers = radeon_resize_buffers;
   radeon->glCtx->Driver.ValidateFramebuffer = radeon_validate_framebuffer;
-  radeon->glCtx->Driver.BlitFramebuffer = _mesa_meta_blit_framebuffer;
+  radeon->glCtx->Driver.BlitFramebuffer = _mesa_meta_BlitFramebuffer;
 }
 
   
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 5ffb55db5e..573eb6c9c1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -48,17 +48,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_screen.h"
 #include "radeon_common.h"
 #include "radeon_span.h"
-#if !RADEON_COMMON
+#if defined(RADEON_R100)
 #include "radeon_context.h"
 #include "radeon_tex.h"
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R200)
 #include "r200_context.h"
 #include "r200_ioctl.h"
 #include "r200_tex.h"
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#elif defined(RADEON_R300)
 #include "r300_context.h"
 #include "r300_tex.h"
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#elif defined(RADEON_R600)
 #include "r600_context.h"
 #include "r700_driconf.h" /* +r6/r7 */
 #include "r600_tex.h"     /* +r6/r7 */
@@ -82,7 +82,7 @@ DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
         DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
 DRI_CONF_OPT_END
 
-#if !RADEON_COMMON	/* R100 */
+#if defined(RADEON_R100)	/* R100 */
 PUBLIC const char __driConfigOptions[] =
 DRI_CONF_BEGIN
     DRI_CONF_SECTION_PERFORMANCE
@@ -109,7 +109,7 @@ DRI_CONF_BEGIN
 DRI_CONF_END;
 static const GLuint __driNConfigOptions = 15;
 
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R200)
 
 PUBLIC const char __driConfigOptions[] =
 DRI_CONF_BEGIN
@@ -147,7 +147,7 @@ extern const struct dri_extension NV_vp_extension[];
 extern const struct dri_extension ATI_fs_extension[];
 extern const struct dri_extension point_extensions[];
 
-#elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
+#elif defined(RADEON_R300) || defined(RADEON_R600)
 
 #define DRI_CONF_FP_OPTIMIZATION_SPEED   0
 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
@@ -220,7 +220,7 @@ static const GLuint __driNConfigOptions = 17;
 
 extern const struct dri_extension gl_20_extension[];
 
-#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
+#endif
 
 extern const struct dri_extension card_extensions[];
 extern const struct dri_extension mm_extensions[];
@@ -337,7 +337,7 @@ radeonFillInModes( __DRIscreenPrivate *psp,
     return (const __DRIconfig **) configs;
 }
 
-#if !RADEON_COMMON
+#if defined(RADEON_R100)
 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
     radeonSetTexOffset,
@@ -350,7 +350,7 @@ static const __DRItexBufferExtension radeonTexBufferExtension = {
 };
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
 static const __DRIallocateExtension r200AllocateExtension = {
     { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
     r200AllocateMemoryMESA,
@@ -370,7 +370,7 @@ static const __DRItexBufferExtension r200TexBufferExtension = {
 };
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#if defined(RADEON_R300)
 static const __DRItexOffsetExtension r300texOffsetExtension = {
     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
    r300SetTexOffset,
@@ -383,7 +383,7 @@ static const __DRItexBufferExtension r300TexBufferExtension = {
 };
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#if defined(RADEON_R600)
 static const __DRItexOffsetExtension r600texOffsetExtension = {
     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
    r600SetTexOffset, /* +r6/r7 */
@@ -1222,22 +1222,22 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
        screen->extensions[i++] = &driMediaStreamCounterExtension.base;
    }
 
-#if !RADEON_COMMON
+#if defined(RADEON_R100)
    screen->extensions[i++] = &radeonTexOffsetExtension.base;
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
    if (IS_R200_CLASS(screen))
       screen->extensions[i++] = &r200AllocateExtension.base;
 
    screen->extensions[i++] = &r200texOffsetExtension.base;
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#if defined(RADEON_R300)
    screen->extensions[i++] = &r300texOffsetExtension.base;
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#if defined(RADEON_R600)
    screen->extensions[i++] = &r600texOffsetExtension.base;
 #endif
 
@@ -1376,22 +1376,22 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
        screen->extensions[i++] = &driMediaStreamCounterExtension.base;
    }
 
-#if !RADEON_COMMON
+#if defined(RADEON_R100)
    screen->extensions[i++] = &radeonTexBufferExtension.base;
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
    if (IS_R200_CLASS(screen))
        screen->extensions[i++] = &r200AllocateExtension.base;
 
    screen->extensions[i++] = &r200TexBufferExtension.base;
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#if defined(RADEON_R300)
    screen->extensions[i++] = &r300TexBufferExtension.base;
 #endif
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#if defined(RADEON_R600)
    screen->extensions[i++] = &r600TexBufferExtension.base;
 #endif
 
@@ -1589,22 +1589,22 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
 static const __DRIconfig **
 radeonInitScreen(__DRIscreenPrivate *psp)
 {
-#if !RADEON_COMMON
+#if defined(RADEON_R100)
    static const char *driver_name = "Radeon";
    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
    static const __DRIversion dri_expected = { 4, 0, 0 };
    static const __DRIversion drm_expected = { 1, 6, 0 };
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R200)
    static const char *driver_name = "R200";
    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
    static const __DRIversion dri_expected = { 4, 0, 0 };
    static const __DRIversion drm_expected = { 1, 6, 0 };
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#elif defined(RADEON_R300)
    static const char *driver_name = "R300";
    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
    static const __DRIversion dri_expected = { 4, 0, 0 };
    static const __DRIversion drm_expected = { 1, 24, 0 };
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#elif defined(RADEON_R600)
    static const char *driver_name = "R600";
    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
    static const __DRIversion dri_expected = { 4, 0, 0 };
@@ -1630,13 +1630,13 @@ radeonInitScreen(__DRIscreenPrivate *psp)
     * Hello chicken.  Hello egg.  How are you two today?
     */
    driInitExtensions( NULL, card_extensions, GL_FALSE );
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
    driInitExtensions( NULL, blend_extensions, GL_FALSE );
    driInitSingleExtension( NULL, ARB_vp_extension );
    driInitSingleExtension( NULL, NV_vp_extension );
    driInitSingleExtension( NULL, ATI_fs_extension );
    driInitExtensions( NULL, point_extensions, GL_FALSE );
-#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
+#elif (defined(RADEON_R300) || defined(RADEON_R600))
    driInitSingleExtension( NULL, gl_20_extension );
 #endif
 
@@ -1684,13 +1684,13 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
     */
    driInitExtensions( NULL, card_extensions, GL_FALSE );
    driInitExtensions( NULL, mm_extensions, GL_FALSE );
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
    driInitExtensions( NULL, blend_extensions, GL_FALSE );
    driInitSingleExtension( NULL, ARB_vp_extension );
    driInitSingleExtension( NULL, NV_vp_extension );
    driInitSingleExtension( NULL, ATI_fs_extension );
    driInitExtensions( NULL, point_extensions, GL_FALSE );
-#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
+#elif (defined(RADEON_R300) || defined(RADEON_R600))
    driInitSingleExtension( NULL, gl_20_extension );
 #endif
 
@@ -1772,13 +1772,13 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 const struct __DriverAPIRec driDriverAPI = {
    .InitScreen      = radeonInitScreen,
    .DestroyScreen   = radeonDestroyScreen,
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
    .CreateContext   = r200CreateContext,
    .DestroyContext  = r200DestroyContext,
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#elif defined(RADEON_R600)
    .CreateContext   = r600CreateContext,
    .DestroyContext  = radeonDestroyContext,
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#elif defined(RADEON_R300)
    .CreateContext   = r300CreateContext,
    .DestroyContext  = radeonDestroyContext,
 #else
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 4e100d854e..0c49c3713a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -55,7 +55,7 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
 /* r200 depth buffer is always tiled - this is the formula
    according to the docs unless I typo'ed in it
 */
-#if defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
 static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb,
 				 GLint x, GLint y)
 {
@@ -106,6 +106,141 @@ static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb,
 }
 #endif
 
+/* r600 tiling
+ * two main types:
+ * - 1D (akin to macro-linear/micro-tiled on older asics)
+ * - 2D (akin to macro-tiled/micro-tiled on older asics)
+ * only 1D tiling is implemented below
+ */
+#if defined(RADEON_R600)
+static inline GLint r600_1d_tile_helper(const struct radeon_renderbuffer * rrb,
+					GLint x, GLint y, GLint is_depth, GLint is_stencil)
+{
+    GLint element_bytes = rrb->cpp;
+    GLint num_samples = 1;
+    GLint tile_width = 8;
+    GLint tile_height = 8;
+    GLint tile_thickness = 1;
+    GLint pitch_elements = rrb->pitch / element_bytes;
+    GLint height = rrb->base.Height;
+    GLint z = 0;
+    GLint sample_number = 0;
+    /* */
+    GLint tile_bytes;
+    GLint tiles_per_row;
+    GLint tiles_per_slice;
+    GLint slice_offset;
+    GLint tile_row_index;
+    GLint tile_column_index;
+    GLint tile_offset;
+    GLint pixel_number = 0;
+    GLint element_offset;
+    GLint offset = 0;
+
+    tile_bytes = tile_width * tile_height * tile_thickness * element_bytes * num_samples;
+    tiles_per_row = pitch_elements / tile_width;
+    tiles_per_slice = tiles_per_row * (height / tile_height);
+    slice_offset = (z / tile_thickness) * tiles_per_slice * tile_bytes;
+    tile_row_index = y / tile_height;
+    tile_column_index = x / tile_width;
+    tile_offset = ((tile_row_index * tiles_per_row) + tile_column_index) * tile_bytes;
+
+    if (is_depth) {
+	    GLint pixel_offset = 0;
+
+	    pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+	    pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0]
+	    pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1]
+	    pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+	    pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2]
+	    pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+	    switch (element_bytes) {
+	    case 2:
+		    pixel_offset = pixel_number * element_bytes * num_samples;
+		    break;
+	    case 4:
+		    /* stencil and depth data are stored separately within a tile.
+		     * stencil is stored in a contiguous tile before the depth tile.
+		     * stencil element is 1 byte, depth element is 3 bytes.
+		     * stencil tile is 64 bytes.
+		     */
+		    if (is_stencil)
+			    pixel_offset = pixel_number * 1 * num_samples;
+		    else
+			    pixel_offset = (pixel_number * 3 * num_samples) + 64;
+		    break;
+	    }
+	    element_offset = pixel_offset + (sample_number * element_bytes);
+    } else {
+	    GLint sample_offset;
+
+	    switch (element_bytes) {
+	    case 1:
+		    pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+		    pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+		    pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2]
+		    pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+		    pixel_number |= ((y >> 0) & 1) << 4; // pn[4] = y[0]
+		    pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+		    break;
+	    case 2:
+		    pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+		    pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+		    pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2]
+		    pixel_number |= ((y >> 0) & 1) << 3; // pn[3] = y[0]
+		    pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1]
+		    pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+		    break;
+	    case 4:
+		    pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+		    pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+		    pixel_number |= ((y >> 0) & 1) << 2; // pn[2] = y[0]
+		    pixel_number |= ((x >> 2) & 1) << 3; // pn[3] = x[2]
+		    pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1]
+		    pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+		    break;
+	    }
+	    sample_offset = sample_number * (tile_bytes / num_samples);
+	    element_offset = sample_offset + (pixel_number * element_bytes);
+    }
+    offset = slice_offset + tile_offset + element_offset;
+    return offset;
+}
+
+/* depth buffers */
+static GLubyte *r600_ptr_depth(const struct radeon_renderbuffer * rrb,
+			       GLint x, GLint y)
+{
+    GLubyte *ptr = rrb->bo->ptr;
+    GLint offset = r600_1d_tile_helper(rrb, x, y, 1, 0);
+    return &ptr[offset];
+}
+
+static GLubyte *r600_ptr_stencil(const struct radeon_renderbuffer * rrb,
+				 GLint x, GLint y)
+{
+    GLubyte *ptr = rrb->bo->ptr;
+    GLint offset = r600_1d_tile_helper(rrb, x, y, 1, 1);
+    return &ptr[offset];
+}
+
+static GLubyte *r600_ptr_color(const struct radeon_renderbuffer * rrb,
+			       GLint x, GLint y)
+{
+    GLubyte *ptr = rrb->bo->ptr;
+    uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
+    GLint offset;
+
+    if (rrb->has_surface || !(rrb->bo->flags & mask)) {
+        offset = x * rrb->cpp + y * rrb->pitch;
+    } else {
+	    offset = r600_1d_tile_helper(rrb, x, y, 0, 0);
+    }
+    return &ptr[offset];
+}
+
+#else
+
 /* radeon tiling on r300-r500 has 4 states,
    macro-linear/micro-linear
    macro-linear/micro-tiled
@@ -197,7 +332,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
     return &ptr[offset];
 }
 
-#ifndef COMPILE_R300
+#endif
+
+#ifndef RADEON_R300
+#ifndef RADEON_R600
 static uint32_t
 z24s8_to_s8z24(uint32_t val)
 {
@@ -210,6 +348,7 @@ s8z24_to_z24s8(uint32_t val)
    return (val >> 24) | (val << 8);
 }
 #endif
+#endif
 
 /*
  * Note that all information needed to access pixels in a renderbuffer
@@ -270,7 +409,11 @@ s8z24_to_z24s8(uint32_t val)
 
 #define TAG(x)    radeon##x##_RGB565
 #define TAG2(x,y) radeon##x##_RGB565##y
+#if defined(RADEON_R600)
+#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#else
 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
+#endif
 #include "spantmp2.h"
 
 /* 16 bit, ARGB1555 color spanline and pixel functions
@@ -280,7 +423,11 @@ s8z24_to_z24s8(uint32_t val)
 
 #define TAG(x)    radeon##x##_ARGB1555
 #define TAG2(x,y) radeon##x##_ARGB1555##y
+#if defined(RADEON_R600)
+#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#else
 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
+#endif
 #include "spantmp2.h"
 
 /* 16 bit, RGBA4 color spanline and pixel functions
@@ -290,7 +437,11 @@ s8z24_to_z24s8(uint32_t val)
 
 #define TAG(x)    radeon##x##_ARGB4444
 #define TAG2(x,y) radeon##x##_ARGB4444##y
+#if defined(RADEON_R600)
+#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#else
 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
+#endif
 #include "spantmp2.h"
 
 /* 32 bit, xRGB8888 color spanline and pixel functions
@@ -300,11 +451,19 @@ s8z24_to_z24s8(uint32_t val)
 
 #define TAG(x)    radeon##x##_xRGB8888
 #define TAG2(x,y) radeon##x##_xRGB8888##y
+#if defined(RADEON_R600)
+#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0xff000000))
+#define PUT_VALUE(_x, _y, d) { \
+   GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off );		\
+   *_ptr = d;								\
+} while (0)
+#else
 #define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0xff000000))
 #define PUT_VALUE(_x, _y, d) { \
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
    *_ptr = d;								\
 } while (0)
+#endif
 #include "spantmp2.h"
 
 /* 32 bit, ARGB8888 color spanline and pixel functions
@@ -314,11 +473,19 @@ s8z24_to_z24s8(uint32_t val)
 
 #define TAG(x)    radeon##x##_ARGB8888
 #define TAG2(x,y) radeon##x##_ARGB8888##y
+#if defined(RADEON_R600)
+#define GET_VALUE(_x, _y) (*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)))
+#define PUT_VALUE(_x, _y, d) { \
+   GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off );		\
+   *_ptr = d;								\
+} while (0)
+#else
 #define GET_VALUE(_x, _y) (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)))
 #define PUT_VALUE(_x, _y, d) { \
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
    *_ptr = d;								\
 } while (0)
+#endif
 #include "spantmp2.h"
 
 /* ================================================================
@@ -339,17 +506,23 @@ s8z24_to_z24s8(uint32_t val)
  */
 #define VALUE_TYPE GLushort
 
-#if defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
 #define WRITE_DEPTH( _x, _y, d )					\
    *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d
+#elif defined(RADEON_R600)
+#define WRITE_DEPTH( _x, _y, d )					\
+   *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = d
 #else
 #define WRITE_DEPTH( _x, _y, d )					\
    *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d
 #endif
 
-#if defined(RADEON_COMMON_FOR_R200)
+#if defined(RADEON_R200)
 #define READ_DEPTH( d, _x, _y )						\
    d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off)
+#elif defined(RADEON_R600)
+#define READ_DEPTH( d, _x, _y )						\
+   d = *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off)
 #else
 #define READ_DEPTH( d, _x, _y )						\
    d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off)
@@ -365,7 +538,7 @@ s8z24_to_z24s8(uint32_t val)
  */
 #define VALUE_TYPE GLuint
 
-#if defined(COMPILE_R300)
+#if defined(RADEON_R300)
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
@@ -374,7 +547,16 @@ do {									\
    tmp |= ((d << 8) & 0xffffff00);					\
    *_ptr = tmp;					\
 } while (0)
-#elif defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R600)
+#define WRITE_DEPTH( _x, _y, d )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off );		\
+   GLuint tmp = *_ptr;				\
+   tmp &= 0xff000000;							\
+   tmp |= ((d) & 0x00ffffff);					\
+   *_ptr = tmp;					\
+} while (0)
+#elif defined(RADEON_R200)
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off );		\
@@ -394,12 +576,17 @@ do {									\
 } while (0)
 #endif
 
-#if defined(COMPILE_R300)
+#if defined(RADEON_R300)
 #define READ_DEPTH( d, _x, _y )						\
   do {									\
     d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \
   }while(0)
-#elif defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R600)
+#define READ_DEPTH( d, _x, _y )						\
+  do {									\
+    d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off)) & 0x00ffffff); \
+  }while(0)
+#elif defined(RADEON_R200)
 #define READ_DEPTH( d, _x, _y )						\
   do {									\
     d = *(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off)) & 0x00ffffff; \
@@ -420,13 +607,27 @@ do {									\
  */
 #define VALUE_TYPE GLuint
 
-#if defined(COMPILE_R300)
+#if defined(RADEON_R300)
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
    *_ptr = d;								\
 } while (0)
-#elif defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R600)
+#define WRITE_DEPTH( _x, _y, d )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off );		\
+   GLuint tmp = *_ptr;				\
+   tmp &= 0xff000000;							\
+   tmp |= (((d) >> 8) & 0x00ffffff);					\
+   *_ptr = tmp;					\
+   _ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off);		\
+   tmp = *_ptr;				\
+   tmp &= 0xffffff00;							\
+   tmp |= (d) & 0xff;							\
+   *_ptr = tmp;					\
+} while (0)
+#elif defined(RADEON_R200)
 #define WRITE_DEPTH( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off );		\
@@ -442,12 +643,18 @@ do {									\
 } while (0)
 #endif
 
-#if defined(COMPILE_R300)
+#if defined(RADEON_R300)
 #define READ_DEPTH( d, _x, _y )						\
   do { \
     d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)));	\
   }while(0)
-#elif defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R600)
+#define READ_DEPTH( d, _x, _y )						\
+  do { \
+    d = ((*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) << 8) & 0xffffff00; \
+    d |= (*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) & 0x000000ff;	\
+  }while(0)
+#elif defined(RADEON_R200)
 #define READ_DEPTH( d, _x, _y )						\
   do { \
     d = s8z24_to_z24s8(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off)));	\
@@ -467,7 +674,7 @@ do {									\
 
 /* 24 bit depth, 8 bit stencil depthbuffer functions
  */
-#ifdef COMPILE_R300
+#ifdef RADEON_R300
 #define WRITE_STENCIL( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off);		\
@@ -476,7 +683,16 @@ do {									\
    tmp |= (d) & 0xff;							\
    *_ptr = tmp;					\
 } while (0)
-#elif defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R600)
+#define WRITE_STENCIL( _x, _y, d )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off);		\
+   GLuint tmp = *_ptr;				\
+   tmp &= 0xffffff00;							\
+   tmp |= (d) & 0xff;							\
+   *_ptr = tmp;					\
+} while (0)
+#elif defined(RADEON_R200)
 #define WRITE_STENCIL( _x, _y, d )					\
 do {									\
    GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x + x_off, _y + y_off);		\
@@ -496,14 +712,21 @@ do {									\
 } while (0)
 #endif
 
-#ifdef COMPILE_R300
+#ifdef RADEON_R300
 #define READ_STENCIL( d, _x, _y )					\
 do {									\
    GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off );		\
    GLuint tmp = *_ptr;				\
    d = tmp & 0x000000ff;						\
 } while (0)
-#elif defined(RADEON_COMMON_FOR_R200)
+#elif defined(RADEON_R600)
+#define READ_STENCIL( d, _x, _y )					\
+do {									\
+   GLuint *_ptr = (GLuint*)r600_ptr_stencil( rrb, _x + x_off, _y + y_off );		\
+   GLuint tmp = *_ptr;				\
+   d = tmp & 0x000000ff;						\
+} while (0)
+#elif defined(RADEON_R200)
 #define READ_STENCIL( d, _x, _y )					\
 do {									\
    GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off );		\
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 9d252aa74c..ae41b90efe 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -833,11 +833,14 @@ static void import_tex_obj_state( r100ContextPtr rmesa,
    cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
    cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
 
-   if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
-      GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
+   if (texobj->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
+      uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0];
       txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
       txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
-      RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.txr[unit] );
+      RADEON_STATECHANGE( rmesa, txr[unit] );
+   }
+
+   if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
       se_coord_fmt |= RADEON_VTX_ST0_NONPARAMETRIC << unit;
    }
    else {
@@ -1114,7 +1117,6 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec
    RADEON_STATECHANGE( rmesa, ctx );
    rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= 
      (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
-
    RADEON_STATECHANGE( rmesa, tcl );
    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index fad3d1ceda..049284ef8c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -659,11 +659,6 @@ static void radeon_teximage(
 			if (dims == 3)
 				_mesa_free(dstImageOffsets);
 		}
-
-		/* SGIS_generate_mipmap */
-		if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-			radeon_generate_mipmap(ctx, target, texObj);
-		}
 	}
 
 	_mesa_unmap_teximage_pbo(ctx, packing);
@@ -792,11 +787,6 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int leve
 							     format, type, pixels, packing))
 				_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage");
 		}
-
-		/* GL_SGIS_generate_mipmap */
-		if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-			radeon_generate_mipmap(ctx, target, texObj);
-		}
 	}
 
 	radeon_teximage_unmap(image);
diff --git a/src/mesa/drivers/dri/s3v/s3v_tex.c b/src/mesa/drivers/dri/s3v/s3v_tex.c
index 9b92519862..ec1182f34f 100644
--- a/src/mesa/drivers/dri/s3v/s3v_tex.c
+++ b/src/mesa/drivers/dri/s3v/s3v_tex.c
@@ -536,24 +536,13 @@ void s3vInitTextureFuncs( GLcontext *ctx )
 #endif
 
 	ctx->Driver.TexEnv = s3vTexEnv;
-	ctx->Driver.ChooseTextureFormat = _mesa_choose_tex_format;
-	ctx->Driver.TexImage1D = _mesa_store_teximage1d;
 	ctx->Driver.TexImage2D = s3vTexImage2D;
-	ctx->Driver.TexImage3D = _mesa_store_teximage3d;
-	ctx->Driver.TexSubImage1D = _mesa_store_texsubimage1d;
 	ctx->Driver.TexSubImage2D = s3vTexSubImage2D;
-	ctx->Driver.TexSubImage3D = _mesa_store_texsubimage3d;
-	ctx->Driver.CopyTexImage1D = _swrast_copy_teximage1d;
-	ctx->Driver.CopyTexImage2D = _swrast_copy_teximage2d;
-	ctx->Driver.CopyTexSubImage1D = _swrast_copy_texsubimage1d;
-	ctx->Driver.CopyTexSubImage2D = _swrast_copy_texsubimage2d;
-	ctx->Driver.CopyTexSubImage3D = _swrast_copy_texsubimage3d;
 	ctx->Driver.BindTexture = s3vBindTexture;
 	ctx->Driver.DeleteTexture = s3vDeleteTexture;
 	ctx->Driver.TexParameter = s3vTexParameter;
 	ctx->Driver.UpdateTexturePalette = 0;
 	ctx->Driver.IsTextureResident = s3vIsTextureResident;
-	ctx->Driver.TestProxyTexImage = _mesa_test_proxy_teximage;
 
 	s3vInitTextureObjects( ctx );
 }
diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c
index a858af30c1..cd499cd5d2 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -43,6 +43,7 @@
 #include "tnl/t_pipeline.h"
 #include "vbo/vbo.h"
 #include "drivers/common/driverfuncs.h"
+#include "drivers/common/meta.h"
 #include "utils.h"
 
 #include "swrast_priv.h"
@@ -62,6 +63,7 @@
 #define need_GL_SGI_color_table
 
 /* sw extensions not associated with some GL version */
+#define need_GL_ARB_draw_elements_base_vertex
 #define need_GL_ARB_shader_objects
 #define need_GL_ARB_vertex_array_object
 #define need_GL_ARB_vertex_program
@@ -95,6 +97,8 @@ const struct dri_extension card_extensions[] =
     { "GL_EXT_histogram",		GL_EXT_histogram_functions },
     { "GL_SGI_color_table",		GL_SGI_color_table_functions },
 
+    { "GL_ARB_depth_clamp",		NULL },
+    { "GL_ARB_draw_elements_base_vertex", GL_ARB_draw_elements_base_vertex_functions },
     { "GL_ARB_shader_objects",		GL_ARB_shader_objects_functions },
     { "GL_ARB_vertex_array_object",	GL_ARB_vertex_array_object_functions },
     { "GL_ARB_vertex_program",		GL_ARB_vertex_program_functions },
@@ -109,6 +113,7 @@ const struct dri_extension card_extensions[] =
     { "GL_EXT_paletted_texture",	GL_EXT_paletted_texture_functions },
     { "GL_EXT_stencil_two_side",	GL_EXT_stencil_two_side_functions },
     { "GL_MESA_resize_buffers",		GL_MESA_resize_buffers_functions },
+    { "GL_NV_depth_clamp",		NULL },
     { "GL_NV_vertex_program",		GL_NV_vertex_program_functions },
     { "GL_NV_fragment_program",		GL_NV_fragment_program_functions },
     { NULL,				NULL }
@@ -645,6 +650,8 @@ driCreateNewContext(__DRIscreen *screen, const __DRIconfig *config,
     _mesa_enable_2_0_extensions(mesaCtx);
     _mesa_enable_2_1_extensions(mesaCtx);
 
+    _mesa_meta_init(mesaCtx);
+
     return ctx;
 }
 
@@ -656,6 +663,7 @@ driDestroyContext(__DRIcontext *ctx)
 
     if (ctx) {
 	mesaCtx = &ctx->Base;
+        _mesa_meta_free(mesaCtx);
 	_swsetup_DestroyContext( mesaCtx );
 	_swrast_DestroyContext( mesaCtx );
 	_tnl_DestroyContext( mesaCtx );
diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c
index 1f7257eaea..f6a48b3ae1 100644
--- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c
+++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c
@@ -176,6 +176,54 @@ logbase2(int n)
 }
 
 
+static void
+tdfxGenerateMipmap(GLcontext *ctx, GLenum target,
+                   struct gl_texture_object *texObj)
+{
+   GLint mipWidth, mipHeight;
+   tdfxMipMapLevel *mip;
+   struct gl_texture_image *mipImage; /* the new/next image */
+   struct gl_texture_image *texImage;
+   const GLint maxLevels = _mesa_max_texture_levels(ctx, texObj->Target);
+   GLint level = texObj->BaseLevel;
+   GLsizei width, height, texelBytes;
+   const tdfxMipMapLevel *mml;
+
+   texImage = _mesa_get_tex_image(ctx, texObj, target, level);
+   assert(!texImage->IsCompressed);
+
+   mml = TDFX_TEXIMAGE_DATA(texImage);
+
+   width = texImage->Width;
+   height = texImage->Height;
+   while (level < texObj->MaxLevel && level < maxLevels - 1) {
+      mipWidth = width / 2;
+      if (!mipWidth) {
+         mipWidth = 1;
+      }
+      mipHeight = height / 2;
+      if (!mipHeight) {
+         mipHeight = 1;
+      }
+      if ((mipWidth == width) && (mipHeight == height)) {
+         break;
+      }
+      ++level;
+      mipImage = _mesa_select_tex_image(ctx, texObj, target, level);
+      mip = TDFX_TEXIMAGE_DATA(mipImage);
+      _mesa_halve2x2_teximage2d(ctx,
+                                texImage,
+                                texelBytes,
+                                mml->width, mml->height,
+                                texImage->Data, mipImage->Data);
+      texImage = mipImage;
+      mml = mip;
+      width = mipWidth;
+      height = mipHeight;
+   }
+}
+
+
 /*
  * Compute various texture image parameters.
  * Input:  w, h - source texture width and height
@@ -1397,45 +1445,6 @@ tdfxTexImage2D(GLcontext *ctx, GLenum target, GLint level,
                                           width, height, 1,
                                           format, type, pixels, packing);
        }
-
-      /* GL_SGIS_generate_mipmap */
-      if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-         GLint mipWidth, mipHeight;
-         tdfxMipMapLevel *mip;
-         struct gl_texture_image *mipImage;
-         const GLint maxLevels = _mesa_max_texture_levels(ctx, texObj->Target);
-   
-         assert(!texImage->IsCompressed);
-   
-         while (level < texObj->MaxLevel && level < maxLevels - 1) {
-            mipWidth = width / 2;
-            if (!mipWidth) {
-               mipWidth = 1;
-            }
-            mipHeight = height / 2;
-            if (!mipHeight) {
-               mipHeight = 1;
-            }
-            if ((mipWidth == width) && (mipHeight == height)) {
-               break;
-            }
-            _mesa_TexImage2D(target, ++level, internalFormat,
-                             mipWidth, mipHeight, border,
-                             format, type,
-                             NULL);
-            mipImage = _mesa_select_tex_image(ctx, texObj, target, level);
-            mip = TDFX_TEXIMAGE_DATA(mipImage);
-            _mesa_halve2x2_teximage2d(ctx,
-                                      texImage,
-                                      texelBytes,
-                                      mml->width, mml->height,
-                                      texImage->Data, mipImage->Data);
-            texImage = mipImage;
-            mml = mip;
-            width = mipWidth;
-            height = mipHeight;
-         }
-      }
     }
 
     RevalidateTexture(ctx, texObj);
@@ -1507,44 +1516,6 @@ tdfxTexSubImage2D(GLcontext *ctx, GLenum target, GLint level,
                                         format, type, pixels, packing);
     }
 
-   /* GL_SGIS_generate_mipmap */
-   if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-      GLint mipWidth, mipHeight;
-      tdfxMipMapLevel *mip;
-      struct gl_texture_image *mipImage;
-      const GLint maxLevels = _mesa_max_texture_levels(ctx, texObj->Target);
-
-      assert(!texImage->IsCompressed);
-
-      width = texImage->Width;
-      height = texImage->Height;
-      while (level < texObj->MaxLevel && level < maxLevels - 1) {
-         mipWidth = width / 2;
-         if (!mipWidth) {
-            mipWidth = 1;
-         }
-         mipHeight = height / 2;
-         if (!mipHeight) {
-            mipHeight = 1;
-         }
-         if ((mipWidth == width) && (mipHeight == height)) {
-            break;
-         }
-         ++level;
-         mipImage = _mesa_select_tex_image(ctx, texObj, target, level);
-         mip = TDFX_TEXIMAGE_DATA(mipImage);
-         _mesa_halve2x2_teximage2d(ctx,
-                                   texImage,
-                                   texelBytes,
-                                   mml->width, mml->height,
-                                   texImage->Data, mipImage->Data);
-         texImage = mipImage;
-         mml = mip;
-         width = mipWidth;
-         height = mipHeight;
-      }
-   }
-
     ti->reloadImages = GL_TRUE; /* signal the image needs to be reloaded */
     fxMesa->new_state |= TDFX_NEW_TEXTURE;  /* XXX this might be a bit much */
 }
@@ -1703,11 +1674,6 @@ tdfxCompressedTexImage2D (GLcontext *ctx, GLenum target,
        MEMCPY(texImage->Data, data, texImage->CompressedSize);
     }
 
-    /* GL_SGIS_generate_mipmap */
-    if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-       assert(!texImage->IsCompressed);
-    }
-
     RevalidateTexture(ctx, texObj);
 
     ti->reloadImages = GL_TRUE;
@@ -1770,11 +1736,6 @@ tdfxCompressedTexSubImage2D( GLcontext *ctx, GLenum target,
                                 texImage->Data);
     }
 
-    /* GL_SGIS_generate_mipmap */
-    if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-       assert(!texImage->IsCompressed);
-    }
-
     RevalidateTexture(ctx, texObj);
 
     ti->reloadImages = GL_TRUE;
@@ -1914,4 +1875,5 @@ void tdfxInitTextureFuncs( struct dd_function_table *functions )
    functions->CompressedTexImage2D	= tdfxCompressedTexImage2D;
    functions->CompressedTexSubImage2D	= tdfxCompressedTexSubImage2D;
    functions->UpdateTexturePalette      = tdfxUpdateTexturePalette;
+   functions->GenerateMipmap            = tdfxGenerateMipmap;
 }
diff --git a/src/mesa/drivers/dri/unichrome/via_tex.c b/src/mesa/drivers/dri/unichrome/via_tex.c
index d2010f0907..54073e7691 100644
--- a/src/mesa/drivers/dri/unichrome/via_tex.c
+++ b/src/mesa/drivers/dri/unichrome/via_tex.c
@@ -818,11 +818,6 @@ static void viaTexImage(GLcontext *ctx,
       }
    }
 
-   /* GL_SGIS_generate_mipmap */
-   if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-      _mesa_generate_mipmap(ctx, target, texObj);
-   }
-
    _mesa_unmap_teximage_pbo(ctx, packing);
 }
author	Nicolai Hähnle <nhaehnle@gmail.com>	2009-09-21 13:26:50 +0200
committer	Nicolai Hähnle <nhaehnle@gmail.com>	2009-09-21 13:26:50 +0200
commit	81c7561d9d3faf70ac22c6a5f3fbea18f53eed92 (patch)
tree	5ec097e0e1fe99804104d3a56923c16edf1533aa /src/mesa/drivers/dri
parent	f02f63997ce65530788a6dfcb28f11790a14d938 (diff)
parent	3083ba38f4c884b32cd0460607b5064b6b7008d2 (diff)