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authorBrian Paul <brianp@vmware.com>2009-01-14 16:26:41 -0700
committerBrian Paul <brianp@vmware.com>2009-01-14 16:49:24 -0700
commit5912cdff3e1f2296b1f5753a008b225bdac4559a (patch)
tree42258399058cadc47a00d18b79f285d0a0431a33 /src/mesa/drivers/dri
parent03188b09e071ace9d9e21ccc56c01e90c0fa8639 (diff)
i965: fix some FBO depth/stencil assertions
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/intel/intel_depthstencil.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_depthstencil.c b/src/mesa/drivers/dri/intel/intel_depthstencil.c
index c2b4d7728b..f43b9aed48 100644
--- a/src/mesa/drivers/dri/intel/intel_depthstencil.c
+++ b/src/mesa/drivers/dri/intel/intel_depthstencil.c
@@ -177,8 +177,11 @@ intel_validate_paired_depth_stencil(GLcontext * ctx,
}
else {
/* Separate depth/stencil buffers, need to interleave now */
- ASSERT(depthRb->Base._BaseFormat == GL_DEPTH_COMPONENT);
- ASSERT(stencilRb->Base._BaseFormat == GL_STENCIL_INDEX);
+ ASSERT(depthRb->Base._BaseFormat == GL_DEPTH_COMPONENT ||
+ depthRb->Base._BaseFormat == GL_DEPTH_STENCIL);
+ ASSERT(stencilRb->Base._BaseFormat == GL_STENCIL_INDEX ||
+ stencilRb->Base._BaseFormat == GL_DEPTH_STENCIL);
+
/* may need to interleave depth/stencil now */
if (depthRb->PairedStencil == stencilRb->Base.Name) {
/* OK, the depth and stencil buffers are already interleaved */