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authorCorbin Simpson <MostAwesomeDude@gmail.com>2010-04-16 00:39:42 -0700
committerCorbin Simpson <MostAwesomeDude@gmail.com>2010-04-16 00:43:18 -0700
commitb1a89ea1abe1c69e3e0abcdfc2b525fe7f727864 (patch)
tree69c2040d87c89634ab93f5bb5b48548f01224efc /src/mesa/drivers
parent2c5b35807eb506a1f7a4fc675f5644ae2f675d84 (diff)
r300/compiler: Fix texture instruction readmasks.
No immediate benefit, it was just bugging me.
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c6
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c24
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h4
3 files changed, 27 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c
index e0c66c4aeb..f3734852cc 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c
@@ -162,7 +162,7 @@ static void update_instruction(struct deadcode_state * s, struct rc_instruction
}
unsigned int srcmasks[3];
- rc_compute_sources_for_writemask(opcode, usedmask, srcmasks);
+ rc_compute_sources_for_writemask(inst, usedmask, srcmasks);
for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) {
unsigned int refmask = 0;
@@ -250,7 +250,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f
for(struct rc_instruction * inst = c->Program.Instructions.Next;
inst != &c->Program.Instructions;
inst = inst->Next, ++ip) {
- const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);\
+ const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
int dead = 1;
if (!opcode->HasDstReg) {
@@ -281,7 +281,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f
else if (inst->U.I.WriteALUResult == RC_ALURESULT_W)
usemask |= RC_MASK_W;
- rc_compute_sources_for_writemask(opcode, usemask, srcmasks);
+ rc_compute_sources_for_writemask(inst, usemask, srcmasks);
for(unsigned int src = 0; src < 3; ++src) {
for(unsigned int chan = 0; chan < 4; ++chan) {
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index cf8602e329..ffc91241ab 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -26,6 +26,7 @@
*/
#include "radeon_opcodes.h"
+#include "radeon_program.h"
#include "radeon_program_constants.h"
@@ -371,10 +372,11 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
};
void rc_compute_sources_for_writemask(
- const struct rc_opcode_info * opcode,
+ const struct rc_instruction *inst,
unsigned int writemask,
unsigned int *srcmasks)
{
+ const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
srcmasks[0] = 0;
srcmasks[1] = 0;
srcmasks[2] = 0;
@@ -406,10 +408,26 @@ void rc_compute_sources_for_writemask(
srcmasks[0] |= RC_MASK_XYZW;
srcmasks[1] |= RC_MASK_XYZW;
break;
- case RC_OPCODE_TEX:
case RC_OPCODE_TXB:
case RC_OPCODE_TXP:
- srcmasks[0] |= RC_MASK_XYZW;
+ srcmasks[0] |= RC_MASK_W;
+ /* Fall through */
+ case RC_OPCODE_TEX:
+ switch (inst->U.I.TexSrcTarget) {
+ case RC_TEXTURE_1D:
+ srcmasks[0] |= RC_MASK_X;
+ break;
+ case RC_TEXTURE_2D:
+ case RC_TEXTURE_RECT:
+ case RC_TEXTURE_1D_ARRAY:
+ srcmasks[0] |= RC_MASK_XY;
+ break;
+ case RC_TEXTURE_3D:
+ case RC_TEXTURE_CUBE:
+ case RC_TEXTURE_2D_ARRAY:
+ srcmasks[0] |= RC_MASK_XYZ;
+ break;
+ }
break;
case RC_OPCODE_DST:
srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
index a3c5b86954..1c9b34df78 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
@@ -227,8 +227,10 @@ static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
return &rc_opcodes[opcode];
}
+struct rc_instruction;
+
void rc_compute_sources_for_writemask(
- const struct rc_opcode_info * opcode,
+ const struct rc_instruction *inst,
unsigned int writemask,
unsigned int *srcmasks);