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authorBrian Paul <brianp@vmware.com>2009-09-09 09:00:58 -0600
committerBrian Paul <brianp@vmware.com>2009-09-09 09:00:58 -0600
commit7bf63473623e01933adc0e8f4464eda8f2860564 (patch)
tree4cfb1b611c999c4b158e6809ee78a02e4d7698b5 /src/mesa/drivers
parent94a8157ef6bf6695cdc66325c9a7698e64f3e37e (diff)
parent0c309bb494b6ee1c403442d1207743f749f95b6e (diff)
Merge branch 'mesa_7_6_branch'
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/common/meta.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_pixel_read.c13
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c7
6 files changed, 28 insertions, 2 deletions
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 6e0905aa49..d1c2232e26 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1512,7 +1512,10 @@ _mesa_meta_draw_pixels(GLcontext *ctx,
if (_mesa_is_color_format(format)) {
/* use more compact format when possible */
- if (format == GL_LUMINANCE || format == GL_LUMINANCE_ALPHA)
+ /* XXX disable special case for GL_LUMINANCE for now to work around
+ * apparent i965 driver bug (see bug #23670).
+ */
+ if (/*format == GL_LUMINANCE ||*/ format == GL_LUMINANCE_ALPHA)
texIntFormat = format;
else
texIntFormat = GL_RGBA;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26a64d6528..a5209ac41b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -390,6 +390,8 @@ struct brw_cached_batch_item {
struct brw_vertex_element {
const struct gl_client_array *glarray;
+ /** The corresponding Mesa vertex attribute */
+ gl_vert_attrib attrib;
/** Size of a complete element */
GLuint element_size;
/** Number of uploaded elements for this input. */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 42961dd4fe..44bb7bd588 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -184,6 +184,7 @@ static void brw_merge_inputs( struct brw_context *brw,
for (i = 0; i < VERT_ATTRIB_MAX; i++) {
brw->vb.inputs[i].glarray = arrays[i];
+ brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
if (arrays[i]->StrideB != 0)
brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 27dabc02f3..765ae5a2fe 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -423,7 +423,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
/* Queue the buffer object up to be uploaded in the next pass,
* when we've decided if we're doing interleaved or not.
*/
- if (i == 0) {
+ if (input->attrib == VERT_ATTRIB_POS) {
/* Position array not properly enabled:
*/
if (input->glarray->StrideB == 0) {
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index bc67f6242a..aef760c015 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -252,6 +252,7 @@ do_blit_readpixels(GLcontext * ctx,
if (!intel_intersect_cliprects(&rect, &src_rect, &box[i]))
continue;
+<<<<<<< HEAD:src/mesa/drivers/dri/intel/intel_pixel_read.c
if (!intelEmitCopyBlit(intel,
src->cpp,
src->pitch, src->buffer, 0, src->tiling,
@@ -265,6 +266,18 @@ do_blit_readpixels(GLcontext * ctx,
UNLOCK_HARDWARE(intel);
return GL_FALSE;
}
+=======
+ intelEmitCopyBlit(intel,
+ src->cpp,
+ src->pitch, src->buffer, 0, src->tiling,
+ rowLength, dst_buffer, dst_offset, GL_FALSE,
+ rect.x1,
+ rect.y1,
+ rect.x1 - src_rect.x1,
+ rect.y2 - src_rect.y2,
+ rect.x2 - rect.x1, rect.y2 - rect.y1,
+ GL_COPY);
+>>>>>>> mesa_7_5_branch:src/mesa/drivers/dri/intel/intel_pixel_read.c
}
}
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 068a3f3379..a86c66a844 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -196,6 +196,13 @@ intel_region_alloc(struct intel_context *intel,
else
height = ALIGN(height, 2);
+ /* If we're untiled, we have to align to 2 rows high because the
+ * data port accesses 2x2 blocks even if the bottom row isn't to be
+ * rendered, so failure to align means we could walk off the end of the
+ * GTT and fault.
+ */
+ height = ALIGN(height, 2);
+
if (expect_accelerated_upload) {
buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
pitch * cpp * height, 64);