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authorRoland Scheidegger <rscheidegger@gmx.ch>2005-01-26 14:20:14 +0000
committerRoland Scheidegger <rscheidegger@gmx.ch>2005-01-26 14:20:14 +0000
commit0cbc25480f3108a9a49277d57ba2b9e2332d3ccd (patch)
tree54ce2bbdbee6ad9fc3eab2726498aacd0e0c8874 /src/mesa
parent8f029f175e839e10f1fa5cadd35ea015eae59d7f (diff)
replace magic number with macro constant RADEON_ZBLOCK16
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state_init.c2
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_reg.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 1dece86208..8db3c88192 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -357,7 +357,7 @@ void radeonInitState( radeonContextPtr rmesa )
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
color_fmt |
- (1<<15));
+ RADEON_ZBLOCK16);
switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
case DRI_CONF_DITHER_XERRORDIFFRESET:
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
index a35aa21a8b..f8c71d6270 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
@@ -1540,6 +1540,7 @@
# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
+# define RADEON_ZBLOCK16 (1 << 15)
#define RADEON_RB3D_COLOROFFSET 0x1c40
# define RADEON_COLOROFFSET_MASK 0xfffffff0
#define RADEON_RB3D_COLORPITCH 0x1c48