diff options
| author | Ben Skeggs <skeggsb@gmail.com> | 2007-12-11 16:02:14 +1100 |
|---|---|---|
| committer | Ben Skeggs <skeggsb@gmail.com> | 2007-12-11 16:02:14 +1100 |
| commit | c23d0f4c501b9e80ba18d6ccf09d4c95353c1a28 (patch) | |
| tree | af46b03b00004e6db55a94d8a90dd2f80ef0ebe3 /src/mesa | |
| parent | b34952c758cf009927e7d7091205e7c13052efad (diff) | |
nv40: allow reading from fragprog result regs
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/pipe/nv40/nv40_fragprog.c | 16 | ||||
| -rw-r--r-- | src/mesa/pipe/nv40/nv40_shader.h | 8 |
2 files changed, 19 insertions, 5 deletions
diff --git a/src/mesa/pipe/nv40/nv40_fragprog.c b/src/mesa/pipe/nv40/nv40_fragprog.c index cc3cb97043..105d7937f3 100644 --- a/src/mesa/pipe/nv40/nv40_fragprog.c +++ b/src/mesa/pipe/nv40/nv40_fragprog.c @@ -85,6 +85,9 @@ emit_src(struct nv40_fpc *fpc, uint32_t *hw, int pos, struct nv40_sreg src) sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT); hw[0] |= (src.index << NV40_FP_OP_INPUT_SRC_SHIFT); break; + case NV40SR_OUTPUT: + sr |= NV40_FP_REG_SRC_HALF; + /* fall-through */ case NV40SR_TEMP: sr |= (NV40_FP_REG_TYPE_TEMP << NV40_FP_REG_TYPE_SHIFT); sr |= (src.index << NV40_FP_REG_SRC_SHIFT); @@ -129,7 +132,7 @@ emit_dst(struct nv40_fpc *fpc, uint32_t *hw, struct nv40_sreg dst) if (dst.index == 1) { fp->writes_depth = 1; } else { - hw[0] |= NV40_FP_OP_UNK0_7; + hw[0] |= NV40_FP_OP_OUT_REG_HALF; } break; case NV40SR_NONE: @@ -213,6 +216,15 @@ tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc) if (fpc->high_temp < src.index) fpc->high_temp = src.index; break; + /* This is clearly insane, but gallium hands us shaders like this. + * Luckily fragprog results are just temp regs.. + */ + case TGSI_FILE_OUTPUT: + if (fsrc->SrcRegister.Index == fpc->colour_id) + return nv40_sr(NV40SR_OUTPUT, 0); + else + return nv40_sr(NV40SR_OUTPUT, 1); + break; default: NOUVEAU_ERR("bad src file\n"); break; @@ -391,6 +403,8 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc, case TGSI_FILE_SAMPLER: unit = fsrc->SrcRegister.Index; break; + case TGSI_FILE_OUTPUT: + break; default: NOUVEAU_ERR("bad src file\n"); return FALSE; diff --git a/src/mesa/pipe/nv40/nv40_shader.h b/src/mesa/pipe/nv40/nv40_shader.h index 207dafd748..01c0652b4d 100644 --- a/src/mesa/pipe/nv40/nv40_shader.h +++ b/src/mesa/pipe/nv40/nv40_shader.h @@ -292,9 +292,9 @@ //== Opcode / Destination selection == #define NV40_FP_OP_PROGRAM_END (1 << 0) #define NV40_FP_OP_OUT_REG_SHIFT 1 -#define NV40_FP_OP_OUT_REG_MASK (31 << 1) +#define NV40_FP_OP_OUT_REG_MASK (63 << 1) /* Needs to be set when writing outputs to get expected result.. */ -#define NV40_FP_OP_UNK0_7 (1 << 7) +#define NV40_FP_OP_OUT_REG_HALF (1 << 7) #define NV40_FP_OP_COND_WRITE_ENABLE (1 << 8) #define NV40_FP_OP_OUTMASK_SHIFT 9 #define NV40_FP_OP_OUTMASK_MASK (0xF << 9) @@ -456,8 +456,8 @@ # define NV40_FP_REG_TYPE_INPUT 1 # define NV40_FP_REG_TYPE_CONST 2 #define NV40_FP_REG_SRC_SHIFT 2 -#define NV40_FP_REG_SRC_MASK (31 << 2) -#define NV40_FP_REG_UNK_0 (1 << 8) +#define NV40_FP_REG_SRC_MASK (63 << 2) +#define NV40_FP_REG_SRC_HALF (1 << 8) #define NV40_FP_REG_SWZ_ALL_SHIFT 9 #define NV40_FP_REG_SWZ_ALL_MASK (255 << 9) #define NV40_FP_REG_SWZ_X_SHIFT 9 |