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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-06-12 21:30:20 -0700
committerEric Anholt <eric@anholt.net>2010-06-12 21:47:32 -0700
commit881ec3a81455f8449d06429811107e1f955f2c60 (patch)
tree1629210db95f73a3de3079ea0fd036a7a303fb27 /src/mesa
parent7ba2ecb32bb80ac67a41c63ddea1846105aaf910 (diff)
i965: Add support for math instructions in the gen6 WM.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 175899b026..34490b7f16 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -966,10 +966,25 @@ void brw_math_16( struct brw_compile *p,
struct brw_reg src,
GLuint precision )
{
+ struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1;
GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1;
+ if (intel->gen >= 6) {
+ insn = next_insn(p, BRW_OPCODE_MATH);
+
+ /* Math is the same ISA format as other opcodes, except that CondModifier
+ * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
+ */
+ insn->header.destreg__conditionalmod = function;
+
+ brw_set_dest(insn, dest);
+ brw_set_src0(insn, src);
+ brw_set_src1(insn, brw_null_reg());
+ return;
+ }
+
/* First instruction:
*/
brw_push_insn_state(p);