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authorAlex Deucher <alexdeucher@gmail.com>2009-11-16 15:03:48 -0500
committerAlex Deucher <alexdeucher@gmail.com>2009-11-16 15:03:48 -0500
commitd683acb101a65d0688bfd0818a0ddb4be16e376d (patch)
tree14445dbfffb6894e814879467010dd9656a91f38 /src/mesa
parent0f060250fc95e63e00ebf9eeb603eed470693221 (diff)
r600: don't force Z order
Let the hw decide (early vs late Z) fixes fdo bug 25092 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 41000dc8ce..d7420678ff 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -202,9 +202,6 @@ static void r700SetDBRenderState(GLcontext * ctx)
SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
- /* XXX not sure if this is required */
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
/* XXX need to enable htile for hiz/s */
SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);