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authorEric Anholt <eric@anholt.net>2011-01-07 14:26:39 -0800
committerEric Anholt <eric@anholt.net>2011-01-07 14:35:42 -0800
commit1d1ad6306d0d55b6ba97d9ecc730d5f919d55df5 (patch)
tree0498a9579e69ce6386ec7a9b3ac4217aadb6bfce /src/mesa
parent46a360b26a4d5e9ff8e00388605799ed60849a03 (diff)
i965: Avoid double-negation of immediate values in the VS.
In general, we have to negate in immediate values we pass in because the src1 negate field in the register description is in the bits3 slot that the 32-bit value is loaded into, so it's ignored by the hardware. However, the src0 negate field is in bits1, so after we'd negated the immediate value loaded in, it would also get negated through the register description. This broke this VP instruction in the position calculation in civ4: MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y; Bug #30156
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_emit.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index a64188afc5..fe9737d043 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1426,11 +1426,10 @@ static struct brw_reg get_arg( struct brw_vs_compile *c,
GET_SWZ(src->Swizzle, 1),
GET_SWZ(src->Swizzle, 2),
GET_SWZ(src->Swizzle, 3));
- }
- /* Note this is ok for non-swizzle instructions:
- */
- reg.negate = src->Negate ? 1 : 0;
+ /* Note this is ok for non-swizzle ARB_vp instructions */
+ reg.negate = src->Negate ? 1 : 0;
+ }
return reg;
}