diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2007-01-17 10:39:50 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2007-01-17 10:39:50 +0800 |
| commit | 747c9129c0b592941b14c290ff3d8ab22ad66acb (patch) | |
| tree | bbf80c50c3ddf49e3c345956556aeccc341412cc /src/mesa | |
| parent | afba8f0d30974bf7fbb9533f23eb2f92d49ac526 (diff) | |
I965: fix bug#9625-get the correct PV for quardstrip
The order of vertices in payload for quardstrip is (0, 1, 3, 2),
so the PV for quardstrip is c->reg.vertex[2].
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.c | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs_emit.c | 10 |
3 files changed, 15 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 9066e42252..73263a5fff 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -82,6 +82,9 @@ static void compile_gs_prog( struct brw_context *brw, case GL_QUADS: brw_gs_quads( &c ); break; + case GL_QUAD_STRIP: + brw_gs_quad_strip( &c ); + break; case GL_LINE_LOOP: brw_gs_lines( &c ); break; @@ -145,7 +148,7 @@ static const GLenum gs_prim[GL_POLYGON+1] = { GL_TRIANGLES, GL_TRIANGLES, GL_QUADS, - GL_QUADS, + GL_QUAD_STRIP, GL_TRIANGLES }; diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index f9aa71d919..29a4e80ce1 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -67,6 +67,7 @@ struct brw_gs_compile { #define ATTR_SIZE (4*4) void brw_gs_quads( struct brw_gs_compile *c ); +void brw_gs_quad_strip( struct brw_gs_compile *c ); void brw_gs_tris( struct brw_gs_compile *c ); void brw_gs_lines( struct brw_gs_compile *c ); void brw_gs_points( struct brw_gs_compile *c ); diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index e4eed36a46..9abb94d82e 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -116,6 +116,16 @@ void brw_gs_quads( struct brw_gs_compile *c ) brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); } +void brw_gs_quad_strip( struct brw_gs_compile *c ) +{ + brw_gs_alloc_regs(c, 4); + + brw_gs_emit_vue(c, c->reg.vertex[2], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[3], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); +} + void brw_gs_tris( struct brw_gs_compile *c ) { brw_gs_alloc_regs(c, 3); |