nv50: update to handle new sampler view state

6 files changed, 188 insertions, 130 deletions

diff --git a/src/gallium/drivers/nv50/nv50_context.h b/src/gallium/drivers/nv50/nv50_context.h
index 7b879851b0..42405c1a89 100644
--- a/src/gallium/drivers/nv50/nv50_context.h
+++ b/src/gallium/drivers/nv50/nv50_context.h
@@ -72,6 +72,17 @@ struct nv50_sampler_stateobj {
 	unsigned tsc[8];
 };
 
+struct nv50_sampler_view {
+	struct pipe_sampler_view pipe;
+	uint32_t tic[8];
+};
+
+static INLINE struct nv50_sampler_view *
+nv50_sampler_view(struct pipe_sampler_view *view)
+{
+	return (struct nv50_sampler_view *)view;
+}
+
 static INLINE unsigned
 get_tile_height(uint32_t tile_mode)
 {
@@ -130,7 +141,7 @@ struct nv50_state {
 	unsigned viewport_bypass;
 	struct nouveau_stateobj *tsc_upload;
 	struct nouveau_stateobj *tic_upload;
-	unsigned miptree_nr[PIPE_SHADER_TYPES];
+	unsigned sampler_view_nr[3];
 	struct nouveau_stateobj *vertprog;
 	struct nouveau_stateobj *fragprog;
 	struct nouveau_stateobj *geomprog;
@@ -170,11 +181,10 @@ struct nv50_context {
 	unsigned vtxbuf_nr;
 	struct pipe_vertex_element vtxelt[PIPE_MAX_ATTRIBS];
 	unsigned vtxelt_nr;
-	struct nv50_sampler_stateobj *sampler[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
-	unsigned sampler_nr[PIPE_SHADER_TYPES];
-	struct nv50_miptree *miptree[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
-	struct pipe_sampler_view *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
-	unsigned miptree_nr[PIPE_SHADER_TYPES];
+	struct nv50_sampler_stateobj *sampler[3][PIPE_MAX_SAMPLERS];
+	unsigned sampler_nr[3];
+	struct pipe_sampler_view *sampler_views[3][PIPE_MAX_SAMPLERS];
+	unsigned sampler_view_nr[3];
 
 	uint16_t vbo_fifo;
 };
@@ -244,6 +254,7 @@ extern void nv50_so_init_sifc(struct nv50_context *nv50,
 
 /* nv50_tex.c */
 extern void nv50_tex_validate(struct nv50_context *);
+extern boolean nv50_tex_construct(struct nv50_sampler_view *view);
 
 /* nv50_transfer.c */
 extern void
diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c
index 2232461b9b..ee54749443 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -464,7 +464,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
 	so_data  (so, 0x00000131 | (NV50_CB_PFP << 12));
 
-	ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, PIPE_SHADER_TYPES*32*32,
+	ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 			     &screen->tic);
 	if (ret) {
 		nv50_screen_destroy(pscreen);
@@ -476,9 +476,9 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 		  NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
 	so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
 		  NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
-	so_data  (so, PIPE_SHADER_TYPES * 32 - 1);
+	so_data  (so, 3 * 32 - 1);
 
-	ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, PIPE_SHADER_TYPES*32*32,
+	ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 			     &screen->tsc);
 	if (ret) {
 		nv50_screen_destroy(pscreen);
diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c
index 8e5f1662ea..dd457c0f00 100644
--- a/src/gallium/drivers/nv50/nv50_state.c
+++ b/src/gallium/drivers/nv50/nv50_state.c
@@ -238,6 +238,9 @@ nv50_sampler_state_create(struct pipe_context *pipe,
 	return (void *)sso;
 }
 
+/* type == 0 for VPs, 1 for GPs, 2 for FPs, which is how the
+ * relevant tesla methods are indexed (NV50TCL_BIND_TSC etc.)
+ */
 static INLINE void
 nv50_sampler_state_bind(struct pipe_context *pipe, unsigned type,
 			unsigned nr, void **sampler)
@@ -253,13 +256,13 @@ nv50_sampler_state_bind(struct pipe_context *pipe, unsigned type,
 static void
 nv50_vp_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **s)
 {
-	nv50_sampler_state_bind(pipe, PIPE_SHADER_VERTEX, nr, s);
+	nv50_sampler_state_bind(pipe, 0, nr, s);
 }
 
 static void
 nv50_fp_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **s)
 {
-	nv50_sampler_state_bind(pipe, PIPE_SHADER_FRAGMENT, nr, s);
+	nv50_sampler_state_bind(pipe, 2, nr, s);
 }
 
 static void
@@ -269,24 +272,21 @@ nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
 }
 
 static INLINE void
-nv50_set_sampler_views(struct pipe_context *pipe,
-		       unsigned type,
+nv50_set_sampler_views(struct pipe_context *pipe, unsigned p,
 		       unsigned nr,
 		       struct pipe_sampler_view **views)
 {
 	struct nv50_context *nv50 = nv50_context(pipe);
 	unsigned i;
 
-	for (i = 0; i < nr; i++) {
-		pipe_sampler_view_reference(&nv50->sampler_views[type][i], views[i]);
-		pipe_texture_reference((void *)&nv50->miptree[type][i], views[i]->texture);
-	}
-	for (i = nr; i < nv50->miptree_nr[type]; i++) {
-		pipe_sampler_view_reference(&nv50->sampler_views[type][i], NULL);
-		pipe_texture_reference((void *)&nv50->miptree[type][i], NULL);
-	}
+	for (i = 0; i < nr; i++)
+		pipe_sampler_view_reference(&nv50->sampler_views[p][i],
+					    views[i]);
 
-	nv50->miptree_nr[type] = nr;
+	for (i = nr; i < nv50->sampler_view_nr[p]; i++)
+		pipe_sampler_view_reference(&nv50->sampler_views[p][i], NULL);
+
+	nv50->sampler_view_nr[p] = nr;
 	nv50->dirty |= NV50_NEW_TEXTURE;
 }
 
@@ -295,7 +295,7 @@ nv50_set_vp_sampler_views(struct pipe_context *pipe,
 			  unsigned nr,
 			  struct pipe_sampler_view **views)
 {
-	nv50_set_sampler_views(pipe, PIPE_SHADER_VERTEX, nr, views);
+	nv50_set_sampler_views(pipe, 0, nr, views);
 }
 
 static void
@@ -303,7 +303,15 @@ nv50_set_fp_sampler_views(struct pipe_context *pipe,
 			  unsigned nr,
 			  struct pipe_sampler_view **views)
 {
-	nv50_set_sampler_views(pipe, PIPE_SHADER_FRAGMENT, nr, views);
+	nv50_set_sampler_views(pipe, 2, nr, views);
+}
+
+static void
+nv50_sampler_view_destroy(struct pipe_context *pipe,
+			  struct pipe_sampler_view *view)
+{
+	pipe_texture_reference(&view->texture, NULL);
+	FREE(nv50_sampler_view(view));
 }
 
 static struct pipe_sampler_view *
@@ -311,26 +319,22 @@ nv50_create_sampler_view(struct pipe_context *pipe,
 			 struct pipe_texture *texture,
 			 const struct pipe_sampler_view *templ)
 {
-	struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
+	struct nv50_sampler_view *view = CALLOC_STRUCT(nv50_sampler_view);
 
-	*view = *templ;
-	view->reference.count = 1;
-	view->texture = NULL;
-	pipe_texture_reference(&view->texture, texture);
-	view->context = pipe;
+	view->pipe = *templ;
+	view->pipe.reference.count = 1;
+	view->pipe.texture = NULL;
+	pipe_texture_reference(&view->pipe.texture, texture);
+	view->pipe.context = pipe;
 
-	return view;
+	if (!nv50_tex_construct(view)) {
+		nv50_sampler_view_destroy(pipe, &view->pipe);
+		return NULL;
+	}
+	return &view->pipe;
 }
 
 
-static void
-nv50_sampler_view_destroy(struct pipe_context *pipe,
-			  struct pipe_sampler_view *view)
-{
-	pipe_texture_reference(&view->texture, NULL);
-	FREE(view);
-}
-
 static void *
 nv50_rasterizer_state_create(struct pipe_context *pipe,
 			     const struct pipe_rasterizer_state *cso)
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c
index efab94cab7..741f8e8f59 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -436,8 +436,8 @@ viewport_uptodate:
 			    1 + 19 * PIPE_SHADER_TYPES + nr * 8,
 			    PIPE_SHADER_TYPES * 2);
 
-		nv50_validate_samplers(nv50, so, PIPE_SHADER_VERTEX);
-		nv50_validate_samplers(nv50, so, PIPE_SHADER_FRAGMENT);
+		nv50_validate_samplers(nv50, so, 0); /* VP samplers */
+		nv50_validate_samplers(nv50, so, 2); /* FP samplers */
 
 		so_method(so, tesla, 0x1334, 1); /* flush TSC */
 		so_data  (so, 0);
diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c
index 9f1a171303..2f2ebc8ec4 100644
--- a/src/gallium/drivers/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nv50/nv50_tex.c
@@ -28,26 +28,16 @@
 #include "util/u_format.h"
 
 #define _MIXED(pf, t0, t1, t2, t3, cr, cg, cb, ca, f)		\
-{                                                       	\
-	PIPE_FORMAT_##pf,					\
+[PIPE_FORMAT_##pf] = (						\
 	NV50TIC_0_0_MAPR_##cr | NV50TIC_0_0_TYPER_##t0 |	\
 	NV50TIC_0_0_MAPG_##cg | NV50TIC_0_0_TYPEG_##t1 |	\
 	NV50TIC_0_0_MAPB_##cb | NV50TIC_0_0_TYPEB_##t2 |	\
 	NV50TIC_0_0_MAPA_##ca | NV50TIC_0_0_TYPEA_##t3 |	\
-	NV50TIC_0_0_FMT_##f					\
-}
+	NV50TIC_0_0_FMT_##f)
 
 #define _(pf, t, cr, cg, cb, ca, f) _MIXED(pf, t, t, t, t, cr, cg, cb, ca, f)
 
-struct nv50_texture_format {
-	enum pipe_format pf;
-	uint32_t hw;
-};
-
-#define NV50_TEX_FORMAT_LIST_SIZE \
-	(sizeof(nv50_tex_format_list) / sizeof(struct nv50_texture_format))
-
-static const struct nv50_texture_format nv50_tex_format_list[] =
+static const uint32_t nv50_texture_formats[PIPE_FORMAT_COUNT] =
 {
 	_(A8R8G8B8_UNORM, UNORM, C2, C1, C0, C3,  8_8_8_8),
 	_(A8R8G8B8_SRGB,  UNORM, C2, C1, C0, C3,  8_8_8_8),
@@ -59,10 +49,12 @@ static const struct nv50_texture_format nv50_tex_format_list[] =
 	_(R5G6B5_UNORM, UNORM, C2, C1, C0, ONE, 5_6_5),
 
 	_(L8_UNORM, UNORM, C0, C0, C0, ONE, 8),
+	_(L8_SRGB,  UNORM, C0, C0, C0, ONE, 8),
 	_(A8_UNORM, UNORM, ZERO, ZERO, ZERO, C0, 8),
 	_(I8_UNORM, UNORM, C0, C0, C0, C0, 8),
 
 	_(A8L8_UNORM, UNORM, C0, C0, C0, C1, 8_8),
+	_(A8L8_SRGB,  UNORM, C0, C0, C0, C1, 8_8),
 
 	_(DXT1_RGB, UNORM, C0, C1, C2, ONE, DXT1),
 	_(DXT1_RGBA, UNORM, C0, C1, C2, C3, DXT1),
@@ -80,117 +72,144 @@ static const struct nv50_texture_format nv50_tex_format_list[] =
 	_(R16G16_UNORM, UNORM, C0, C1, ZERO, ONE, 16_16),
 
 	_MIXED(Z32_FLOAT, FLOAT, UINT, UINT, UINT, C0, C0, C0, ONE, 32_DEPTH)
-
 };
 
 #undef _
 #undef _MIXED
 
-static int
-nv50_tex_construct(struct nv50_context *nv50, struct nouveau_stateobj *so,
-		   struct nv50_miptree *mt, int unit, unsigned p)
+static INLINE uint32_t
+nv50_tic_swizzle(uint32_t tc, unsigned swz)
+{
+	switch (swz) {
+	case PIPE_SWIZZLE_RED:
+		return (tc & NV50TIC_0_0_MAPR_MASK) >> NV50TIC_0_0_MAPR_SHIFT;
+	case PIPE_SWIZZLE_GREEN:
+		return (tc & NV50TIC_0_0_MAPG_MASK) >> NV50TIC_0_0_MAPG_SHIFT;
+	case PIPE_SWIZZLE_BLUE:
+		return (tc & NV50TIC_0_0_MAPB_MASK) >> NV50TIC_0_0_MAPB_SHIFT;
+	case PIPE_SWIZZLE_ALPHA:
+		return (tc & NV50TIC_0_0_MAPA_MASK) >> NV50TIC_0_0_MAPA_SHIFT;
+	case PIPE_SWIZZLE_ONE:
+		return 7;
+	case PIPE_SWIZZLE_ZERO:
+	default:
+		return 0;
+	}
+}
+
+boolean
+nv50_tex_construct(struct nv50_sampler_view *view)
 {
-	unsigned i;
-	uint32_t mode;
 	const struct util_format_description *desc;
+	struct nv50_miptree *mt = nv50_miptree(view->pipe.texture);
+	uint32_t swz[4], *tic = view->tic;
 
-	for (i = 0; i < NV50_TEX_FORMAT_LIST_SIZE; i++)
-		if (nv50_tex_format_list[i].pf == mt->base.base.format)
-			break;
-	if (i == NV50_TEX_FORMAT_LIST_SIZE)
-                return 1;
-
-	if (nv50->sampler[p][unit]->normalized)
-		mode = 0x50001000 | (1 << 31);
-	else {
-		mode = 0x50001000 | (7 << 14);
-		assert(mt->base.base.target == PIPE_TEXTURE_2D);
-	}
+	tic[0] = nv50_texture_formats[mt->base.base.format];
 
-	mode |= ((mt->base.bo->tile_mode & 0x0f) << 22) |
-		((mt->base.bo->tile_mode & 0xf0) << 21);
+	swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r);
+	swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g);
+	swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b);
+	swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a);
+	view->tic[0] = (tic[0] &  ~NV50TIC_0_0_SWIZZLE_MASK) |
+		(swz[0] << NV50TIC_0_0_MAPR_SHIFT) |
+		(swz[1] << NV50TIC_0_0_MAPG_SHIFT) |
+		(swz[2] << NV50TIC_0_0_MAPB_SHIFT) |
+		(swz[3] << NV50TIC_0_0_MAPA_SHIFT);
 
-	desc = util_format_description(mt->base.base.format);
-	assert(desc);
+	tic[2] = 0x50001000;
+	tic[2] |= ((mt->base.bo->tile_mode & 0x0f) << 22) |
+		  ((mt->base.bo->tile_mode & 0xf0) << 21);
 
+	desc = util_format_description(mt->base.base.format);
 	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		mode |= 0x0400;
+		tic[2] |= NV50TIC_0_2_COLORSPACE_SRGB;
 
 	switch (mt->base.base.target) {
 	case PIPE_TEXTURE_1D:
+		tic[2] |= NV50TIC_0_2_TARGET_1D;
 		break;
 	case PIPE_TEXTURE_2D:
-		mode |= (1 << 14);
+		tic[2] |= NV50TIC_0_2_TARGET_2D;
 		break;
 	case PIPE_TEXTURE_3D:
-		mode |= (2 << 14);
+		tic[2] |= NV50TIC_0_2_TARGET_3D;
 		break;
 	case PIPE_TEXTURE_CUBE:
-		mode |= (3 << 14);
+		tic[2] |= NV50TIC_0_2_TARGET_CUBE;
 		break;
 	default:
-		assert(!"unsupported texture target");
-		break;
+		NOUVEAU_ERR("invalid texture target: %d\n",
+			    mt->base.base.target);
+		return FALSE;
 	}
 
-	so_data (so, nv50_tex_format_list[i].hw);
-	so_reloc(so, mt->base.bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW |
-		 NOUVEAU_BO_RD, 0, 0);
-	so_data (so, mode);
-	so_data (so, 0x00300000);
-	so_data (so, mt->base.base.width0 | (1 << 31));
-	so_data (so, (mt->base.base.last_level << 28) |
-		 (mt->base.base.depth0 << 16) | mt->base.base.height0);
-	so_data (so, 0x03000000);
-	so_data (so, mt->base.base.last_level << 4);
-
-	return 0;
-}
+	tic[3] = 0x00300000;
+
+	tic[4] = (1 << 31) | mt->base.base.width0;
+	tic[5] = (mt->base.base.last_level << 28) |
+		(mt->base.base.depth0 << 16) | mt->base.base.height0;
+
+	tic[6] = 0x03000000;
 
-#ifndef NV50TCL_BIND_TIC
-#define NV50TCL_BIND_TIC(n) (0x1448 + 8 * n)
-#endif
+	tic[7] = (view->pipe.num_levels - view->pipe.first_level - 1) << 4;
+	tic[7] |= view->pipe.first_level;
+
+	return TRUE;
+}
 
-static boolean
+static int
 nv50_validate_textures(struct nv50_context *nv50, struct nouveau_stateobj *so,
 		       unsigned p)
 {
-	static const unsigned p_remap[PIPE_SHADER_TYPES] = { 0, 2, 1 };
-
 	struct nouveau_grobj *eng2d = nv50->screen->eng2d;
 	struct nouveau_grobj *tesla = nv50->screen->tesla;
-	unsigned unit, j, p_hw = p_remap[p];
+	unsigned unit, j;
+
+	const unsigned rll = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW;
+	const unsigned rlh = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH
+		| NOUVEAU_BO_OR;
 
 	nv50_so_init_sifc(nv50, so, nv50->screen->tic, NOUVEAU_BO_VRAM,
-			  p * (32 * 8 * 4), nv50->miptree_nr[p] * 8 * 4);
+			  p * (32 * 8 * 4), nv50->sampler_view_nr[p] * 8 * 4);
 
-	for (unit = 0; unit < nv50->miptree_nr[p]; ++unit) {
-		struct nv50_miptree *mt = nv50->miptree[p][unit];
+	for (unit = 0; unit < nv50->sampler_view_nr[p]; ++unit) {
+		struct nv50_sampler_view *view =
+			nv50_sampler_view(nv50->sampler_views[p][unit]);
 
 		so_method(so, eng2d, NV50_2D_SIFC_DATA | (2 << 29), 8);
-		if (mt) {
-			if (nv50_tex_construct(nv50, so, mt, unit, p))
-				return FALSE;
+		if (view) {
+			uint32_t tic2 = view->tic[2];
+			struct nv50_miptree *mt =
+				nv50_miptree(view->pipe.texture);
+
+			if (nv50->sampler[p][unit]->normalized)
+				tic2 |= NV50TIC_0_2_NORMALIZED_COORDS;
+
+			so_data  (so, view->tic[0]);
+			so_reloc (so, mt->base.bo, 0, rll, 0, 0);
+			so_reloc (so, mt->base.bo, 0, rlh, tic2, tic2);
+			so_datap (so, &view->tic[3], 5);
+
 			/* Set TEX insn $t src binding $unit in program type p
 			 * to TIC, TSC entry (32 * p + unit), mark valid (1).
 			 */
-			so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1);
+			so_method(so, tesla, NV50TCL_BIND_TIC(p), 1);
 			so_data  (so, ((32 * p + unit) << 9) | (unit << 1) | 1);
 		} else {
 			for (j = 0; j < 8; ++j)
 				so_data(so, 0);
-			so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1);
+			so_method(so, tesla, NV50TCL_BIND_TIC(p), 1);
 			so_data  (so, (unit << 1) | 0);
 		}
 	}
 
-	for (; unit < nv50->state.miptree_nr[p]; unit++) {
+	for (; unit < nv50->state.sampler_view_nr[p]; unit++) {
 		/* Make other bindings invalid. */
-		so_method(so, tesla, NV50TCL_BIND_TIC(p_hw), 1);
+		so_method(so, tesla, NV50TCL_BIND_TIC(p), 1);
 		so_data  (so, (unit << 1) | 0);
 	}
 
-	nv50->state.miptree_nr[p] = nv50->miptree_nr[p];
+	nv50->state.sampler_view_nr[p] = nv50->sampler_view_nr[p];
 	return TRUE;
 }
 
@@ -199,21 +218,23 @@ nv50_tex_validate(struct nv50_context *nv50)
 {
 	struct nouveau_stateobj *so;
 	struct nouveau_grobj *tesla = nv50->screen->tesla;
-	unsigned p, start, push, nrlc;
-
-	for (nrlc = 0, start = 0, push = 0, p = 0; p < PIPE_SHADER_TYPES; ++p) {
-		start += MAX2(nv50->miptree_nr[p], nv50->state.miptree_nr[p]);
-		push += MAX2(nv50->miptree_nr[p], nv50->state.miptree_nr[p]);
-		nrlc += nv50->miptree_nr[p];
+	unsigned p, m = 0, d = 0, r = 0;
+
+	for (p = 0; p < 3; ++p) {
+		unsigned nr = MAX2(nv50->sampler_view_nr[p],
+				   nv50->state.sampler_view_nr[p]);
+		m += nr;
+		d += nr;
+		r += nv50->sampler_view_nr[p];
 	}
-	start = start * 2 + 4 * PIPE_SHADER_TYPES + 2;
-	push = push * 9 + 19 * PIPE_SHADER_TYPES + 2;
-	nrlc = nrlc * 2 + 2 * PIPE_SHADER_TYPES;
+	m = m * 2 + 3 * 4 + 1;
+	d = d * 9 + 3 * 19 + 1;
+	r = r * 2 + 3 * 2;
 
-	so = so_new(start, push, nrlc);
+	so = so_new(m, d, r);
 
-	if (nv50_validate_textures(nv50, so, PIPE_SHADER_VERTEX) == FALSE ||
-	    nv50_validate_textures(nv50, so, PIPE_SHADER_FRAGMENT) == FALSE) {
+	if (nv50_validate_textures(nv50, so, 0) == FALSE ||
+	    nv50_validate_textures(nv50, so, 2) == FALSE) {
 		so_ref(NULL, &so);
 
 		NOUVEAU_ERR("failed tex validate\n");
diff --git a/src/gallium/drivers/nv50/nv50_texture.h b/src/gallium/drivers/nv50/nv50_texture.h
index b870302019..3475d3e432 100644
--- a/src/gallium/drivers/nv50/nv50_texture.h
+++ b/src/gallium/drivers/nv50/nv50_texture.h
@@ -7,7 +7,9 @@
  */
 
 /* Texture image control block */
+#define NV50TIC_0_0_SWIZZLE_MASK                                  0x3ffc0000
 #define NV50TIC_0_0_MAPA_MASK                                     0x38000000
+#define NV50TIC_0_0_MAPA_SHIFT                                            27
 #define NV50TIC_0_0_MAPA_ZERO                                     0x00000000
 #define NV50TIC_0_0_MAPA_C0                                       0x10000000
 #define NV50TIC_0_0_MAPA_C1                                       0x18000000
@@ -15,6 +17,7 @@
 #define NV50TIC_0_0_MAPA_C3                                       0x28000000
 #define NV50TIC_0_0_MAPA_ONE                                      0x38000000
 #define NV50TIC_0_0_MAPB_MASK                                     0x07000000
+#define NV50TIC_0_0_MAPB_SHIFT                                            24
 #define NV50TIC_0_0_MAPB_ZERO                                     0x00000000
 #define NV50TIC_0_0_MAPB_C0                                       0x02000000
 #define NV50TIC_0_0_MAPB_C1                                       0x03000000
@@ -22,6 +25,7 @@
 #define NV50TIC_0_0_MAPB_C3                                       0x05000000
 #define NV50TIC_0_0_MAPB_ONE                                      0x07000000
 #define NV50TIC_0_0_MAPG_MASK                                     0x00e00000
+#define NV50TIC_0_0_MAPG_SHIFT                                            21
 #define NV50TIC_0_0_MAPG_ZERO                                     0x00000000
 #define NV50TIC_0_0_MAPG_C0                                       0x00400000
 #define NV50TIC_0_0_MAPG_C1                                       0x00600000
@@ -29,6 +33,7 @@
 #define NV50TIC_0_0_MAPG_C3                                       0x00a00000
 #define NV50TIC_0_0_MAPG_ONE                                      0x00e00000
 #define NV50TIC_0_0_MAPR_MASK                                     0x001c0000
+#define NV50TIC_0_0_MAPR_SHIFT                                            18
 #define NV50TIC_0_0_MAPR_ZERO                                     0x00000000
 #define NV50TIC_0_0_MAPR_C0                                       0x00080000
 #define NV50TIC_0_0_MAPR_C1                                       0x000c0000
@@ -89,22 +94,39 @@
 #define NV50TIC_0_1_OFFSET_LOW_MASK                               0xffffffff
 #define NV50TIC_0_1_OFFSET_LOW_SHIFT                                       0
 
-#define NV50TIC_0_2_UNKNOWN_MASK                                  0xffffffff
+#define NV50TIC_0_2_COLORSPACE_SRGB                               0x00000400
+#define NV50TIC_0_2_TARGET_1D                                     0x00000000
+#define NV50TIC_0_2_TARGET_2D                                     0x00004000
+#define NV50TIC_0_2_TARGET_3D                                     0x00008000
+#define NV50TIC_0_2_TARGET_CUBE                                   0x0000c000
+#define NV50TIC_0_2_TARGET_1D_ARRAY                               0x00010000
+#define NV50TIC_0_2_TARGET_2D_ARRAY                               0x00014000
+#define NV50TIC_0_2_TARGET_BUFFER                                 0x00018000
+#define NV50TIC_0_2_TARGET_RECT                                   0x0001c000
+/* #define NV50TIC_0_0_TILE_MODE_LINEAR                           0x00040000 */
+#define NV50TIC_0_2_TILE_MODE_Y_MASK                              0x01c00000
+#define NV50TIC_0_2_TILE_MODE_Y_SHIFT                                     22
+#define NV50TIC_0_2_TILE_MODE_Z_MASK                              0x0e000000
+#define NV50TIC_0_2_TILE_MODE_Z_SHIFT                                     25
+#define NV50TIC_0_2_NORMALIZED_COORDS                             0x80000000
 
 #define NV50TIC_0_3_UNKNOWN_MASK                                  0xffffffff
 
 #define NV50TIC_0_4_WIDTH_MASK                                    0x0000ffff
 #define NV50TIC_0_4_WIDTH_SHIFT                                            0
 
-#define NV50TIC_0_5_DEPTH_MASK                                    0xffff0000
+#define NV50TIC_0_5_LAST_LEVEL_MASK                               0xf0000000
+#define NV50TIC_0_5_LAST_LEVEL_SHIFT                                      28
+#define NV50TIC_0_5_DEPTH_MASK                                    0x0fff0000
 #define NV50TIC_0_5_DEPTH_SHIFT                                           16
 #define NV50TIC_0_5_HEIGHT_MASK                                   0x0000ffff
 #define NV50TIC_0_5_HEIGHT_SHIFT                                           0
-
 #define NV50TIC_0_6_UNKNOWN_MASK                                  0xffffffff
 
-#define NV50TIC_0_7_OFFSET_HIGH_MASK                              0xffffffff
-#define NV50TIC_0_7_OFFSET_HIGH_SHIFT                                      0
+#define NV50TIC_0_7_BASE_LEVEL_MASK                               0x0000000f
+#define NV50TIC_0_7_BASE_LEVEL_SHIFT                                       0
+#define NV50TIC_0_7_MAX_LEVEL_MASK                                0x000000f0
+#define NV50TIC_0_7_MAX_LEVEL_SHIFT                                        4
 
 /* Texture sampler control block */
 #define NV50TSC_1_0_WRAPS_MASK                                   0x00000007