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authorAlex Deucher <alexdeucher@gmail.com>2010-04-26 13:45:01 -0400
committerAlex Deucher <alexdeucher@gmail.com>2010-04-26 13:45:01 -0400
commita53e8b7defd9c169a1a98d04d755d3f578292691 (patch)
treeda74b6662f001c83dd7969f27ebbeda8e16c902d /src
parent06574e45b418dab1ec106773c92b7d9e5af45c81 (diff)
r600: avoid setting invalid bit on r7xx for blits
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 244fdc4ffb..172f85eb26 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -344,6 +344,10 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
return;
}
+ /* must be 0 on r7xx */
+ if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+ CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
+
SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
CB_COLOR0_INFO__FORMAT_mask);
SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);