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authorEric Anholt <eric@anholt.net>2010-12-09 10:03:49 -0800
committerEric Anholt <eric@anholt.net>2010-12-09 11:11:04 -0800
commitcfcc2ef587fad91ad1dff1abbd42886dbe9cc095 (patch)
treefef693582897dc077435a302e41cd755f3b42756 /src
parent30f25a10190632a971e2b214c443e54afa463ead (diff)
i965: Set render_cache_read_write surface state bit on gen6 constant surfs.
This is said to be required in the spec, even when you aren't doing writes.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_structs.h5
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c4
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 0e1f3c9bb8..d341187c1b 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1179,6 +1179,11 @@ struct brw_surface_state
GLuint cube_pos_x:1;
GLuint cube_neg_x:1;
GLuint pad:4;
+ /* Required on gen6 for surfaces accessed through render cache messages.
+ */
+ GLuint render_cache_read_write:1;
+ /* Ironlake and newer: instead of replicating one of the texels */
+ GLuint cube_corner_average:1;
GLuint mipmap_layout_mode:1;
GLuint vert_line_stride_ofs:1;
GLuint vert_line_stride:1;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 76fc94df1f..fb0e34e94f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -274,6 +274,7 @@ brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo **out_bo,
uint32_t *out_offset)
{
+ struct intel_context *intel = &brw->intel;
const GLint w = width - 1;
struct brw_surface_state surf;
void *map;
@@ -284,6 +285,9 @@ brw_create_constant_surface(struct brw_context *brw,
surf.ss0.surface_type = BRW_SURFACE_BUFFER;
surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+ if (intel->gen >= 6)
+ surf.ss0.render_cache_read_write = 1;
+
assert(bo);
surf.ss1.base_addr = bo->offset; /* reloc */