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authorEric Anholt <eric@anholt.net>2009-08-12 19:40:27 -0700
committerEric Anholt <eric@anholt.net>2009-08-19 09:19:06 -0700
commitb053474378633249be0e9f24010650ffb816229a (patch)
treeb19edd39515d0fb35bab03c231ad36141cdb985d /src
parent947df2e5a8e4e701db67219179fb9953df8ff6e6 (diff)
intel: Align untiled region height to 2 according to 965 docs.
This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 497f796764..068a3f3379 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -181,10 +181,20 @@ intel_region_alloc(struct intel_context *intel,
dri_bo *buffer;
struct intel_region *region;
+ /* If we're tiled, our allocations are in 8 or 32-row blocks, so
+ * failure to align our height means that we won't allocate enough pages.
+ *
+ * If we're untiled, we still have to align to 2 rows high because the
+ * data port accesses 2x2 blocks even if the bottom row isn't to be
+ * rendered, so failure to align means we could walk off the end of the
+ * GTT and fault.
+ */
if (tiling == I915_TILING_X)
height = ALIGN(height, 8);
else if (tiling == I915_TILING_Y)
height = ALIGN(height, 32);
+ else
+ height = ALIGN(height, 2);
if (expect_accelerated_upload) {
buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",