summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/mesa/drivers/dri/i915/i830_context.h3
-rw-r--r--src/mesa/drivers/dri/i915/i830_vtbl.c43
2 files changed, 36 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h
index b755d48678..d7eb9c2d44 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -34,7 +34,8 @@
#define I830_FALLBACK_COLORMASK 0x2000
#define I830_FALLBACK_STENCIL 0x4000
#define I830_FALLBACK_STIPPLE 0x8000
-#define I830_FALLBACK_LOGICOP 0x10000
+#define I830_FALLBACK_LOGICOP 0x20000
+#define I830_FALLBACK_DRAW_OFFSET 0x200000
#define I830_UPLOAD_CTX 0x1
#define I830_UPLOAD_BUFFERS 0x2
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index a8df77c600..be96419ff1 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -496,15 +496,13 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- state->draw_region->draw_offset);
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- state->depth_region->draw_offset);
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
}
OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
@@ -598,6 +596,7 @@ i830_set_draw_region(struct intel_context *intel,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
GLuint value;
struct i830_hw_state *state = &i830->state;
+ uint32_t draw_x, draw_y;
if (state->draw_region != color_regions[0]) {
intel_region_release(&state->draw_region);
@@ -652,14 +651,40 @@ i830_set_draw_region(struct intel_context *intel,
}
state->Buffer[I830_DESTREG_DV1] = value;
+ /* We set up the drawing rectangle to be offset into the color
+ * region's location in the miptree. If it doesn't match with
+ * depth's offsets, we can't render to it.
+ *
+ * (Well, not actually true -- the hw grew a bit to let depth's
+ * offset get forced to 0,0. We may want to use that if people are
+ * hitting that case. Also, some configurations may be supportable
+ * by tweaking the start offset of the buffers around, which we
+ * can't do in general due to tiling)
+ */
+ FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
+ (depth_region && color_regions[0]) &&
+ (depth_region->draw_x != color_regions[0]->draw_x ||
+ depth_region->draw_y != color_regions[0]->draw_y));
+
+ if (color_regions[0]) {
+ draw_x = color_regions[0]->draw_x;
+ draw_y = color_regions[0]->draw_y;
+ } else if (depth_region) {
+ draw_x = depth_region->draw_x;
+ draw_y = depth_region->draw_y;
+ } else {
+ draw_x = 0;
+ draw_y = 0;
+ }
+
state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
- state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+ state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
state->Buffer[I830_DESTREG_DRAWRECT3] =
- (ctx->DrawBuffer->Width & 0xffff) |
- (ctx->DrawBuffer->Height << 16);
- state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
- state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
+ ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
+ ((ctx->DrawBuffer->Height + draw_y) << 16);
+ state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
+ state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
}