diff options
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_regions.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 497f796764..068a3f3379 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -181,10 +181,20 @@ intel_region_alloc(struct intel_context *intel, dri_bo *buffer; struct intel_region *region; + /* If we're tiled, our allocations are in 8 or 32-row blocks, so + * failure to align our height means that we won't allocate enough pages. + * + * If we're untiled, we still have to align to 2 rows high because the + * data port accesses 2x2 blocks even if the bottom row isn't to be + * rendered, so failure to align means we could walk off the end of the + * GTT and fault. + */ if (tiling == I915_TILING_X) height = ALIGN(height, 8); else if (tiling == I915_TILING_Y) height = ALIGN(height, 32); + else + height = ALIGN(height, 2); if (expect_accelerated_upload) { buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", |