diff options
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_state.c | 32 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_common.c | 25 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_common.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state.c | 25 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/server/radeon_reg.h | 3 |
5 files changed, 30 insertions, 56 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 4d052e246e..af60861bbb 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -764,36 +764,6 @@ static void r200PolygonOffset( GLcontext *ctx, rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32; } -static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLint i; - BATCH_LOCALS(&rmesa->radeon); - drm_radeon_stipple_t stipple; - - radeon_firevertices(&rmesa->radeon); - - BEGIN_BATCH_NO_AUTOSTATE(35); - - OUT_BATCH(CP_PACKET0(R200_RE_STIPPLE_ADDR, 0)); - OUT_BATCH(0x00000000); - - OUT_BATCH(CP_PACKET0_ONE(R200_RE_STIPPLE_DATA, 31)); - - /* Must flip pattern upside down. - */ - for ( i = 31 ; i >= 0; i--) { - OUT_BATCH(((GLuint *) mask)[i]); - } - - END_BATCH(); - - - /* FIXME: Use window x,y offsets into stipple RAM. - */ - stipple.mask = rmesa->state.stipple.mask; -} - static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -2532,7 +2502,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->LogicOpcode = r200LogicOpCode; functions->PolygonMode = r200PolygonMode; functions->PolygonOffset = r200PolygonOffset; - functions->PolygonStipple = r200PolygonStipple; + functions->PolygonStipple = radeonPolygonStipple; functions->PointParameterfv = r200PointParameter; functions->PointSize = r200PointSize; functions->RenderMode = r200RenderMode; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index bed75f3d73..e760279d4a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -273,6 +273,31 @@ void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) } } +void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + GLint i; + BATCH_LOCALS(radeon); + + radeon_firevertices(radeon); + + BEGIN_BATCH_NO_AUTOSTATE(35); + + OUT_BATCH(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); + OUT_BATCH(0x00000000); + + OUT_BATCH(CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31)); + + /* Must flip pattern upside down. + */ + for ( i = 31 ; i >= 0; i--) { + OUT_BATCH(((GLuint *) mask)[i]); + } + + END_BATCH(); +} + + /* ================================================================ * SwapBuffers with client-side throttling diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index a9e1ca49eb..e2a65f46f6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -10,6 +10,7 @@ void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h); +void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ); void radeonWaitForIdleLocked(radeonContextPtr radeon); extern uint32_t radeonGetAge(radeonContextPtr radeon); diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 56f82bdb0b..9d877cb751 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -550,31 +550,6 @@ static void radeonPolygonOffset( GLcontext *ctx, rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32; } -static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - GLuint i; - drm_radeon_stipple_t stipple; - - /* Must flip pattern upside down. - */ - for ( i = 0 ; i < 32 ; i++ ) { - rmesa->state.stipple.mask[31 - i] = ((GLuint *) mask)[i]; - } - - /* TODO: push this into cmd mechanism - */ - radeon_firevertices(&rmesa->radeon); - LOCK_HARDWARE( &rmesa->radeon ); - - /* FIXME: Use window x,y offsets into stipple RAM. - */ - stipple.mask = rmesa->state.stipple.mask; - drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, - &stipple, sizeof(drm_radeon_stipple_t) ); - UNLOCK_HARDWARE( &rmesa->radeon ); -} - static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h index c9054606eb..e81d7fdcd0 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h +++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h @@ -1663,6 +1663,9 @@ # define RADEON_FORCE_Z_DIRTY (1 << 29) # define RADEON_Z_WRITE_ENABLE (1 << 30) # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) + +#define RADEON_RE_STIPPLE_ADDR 0x1cc8 +#define RADEON_RE_STIPPLE_DATA 0x1ccc #define RADEON_RE_LINE_PATTERN 0x1cd0 # define RADEON_LINE_PATTERN_MASK 0x0000ffff # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 |